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参数资料
型号： PIC18F8720T-E/PT
厂商： Microchip Technology
文件页数： 120/165页
文件大小： 0K
描述： IC PIC MCU FLASH 64KX16 80TQFP
标准包装： 1,200
系列： PIC® 18F
核心处理器： PIC
芯体尺寸： 8-位
速度： 25MHz
连通性： EBI/EMI，I²C，SPI，UART/USART
外围设备： 欠压检测/复位，LVD，POR，PWM，WDT
输入/输出数： 68
程序存储器容量： 128KB（64K x 16）
程序存储器类型： 闪存
EEPROM 大小： 1K x 8
RAM 容量： 3.75K x 8
电压 - 电源 (Vcc/Vdd)： 4.2 V ~ 5.5 V
数据转换器： A/D 16x10b
振荡器型： 外部
工作温度： -40°C ~ 125°C
封装/外壳： 80-TQFP
包装： 带卷 (TR)
配用： XLT80PT3-ND - SOCKET TRAN ICE 80MQFP/TQFP
AC164320-ND - MODULE SKT MPLAB PM3 80TQFP
AC174011-ND - MODULE SKT PROMATEII 80TQFP
PIC18F6520/8520/6620/8620/6720/8720
DS39609B-page 56
2004 Microchip Technology Inc.
4.10
Access Bank
The Access Bank is an architectural enhancement,
which is very useful for C compiler code optimization.
The techniques used by the C compiler may also be
useful for programs written in assembly.
This data memory region can be used for:
Intermediate computational values
Local variables of subroutines
Faster context saving/switching of variables
Common variables
Faster evaluation/control of SFRs (no banking)
The Access Bank is comprised of the upper 160 bytes
in Bank 15 (SFRs) and the lower 96 bytes in Bank 0.
These two sections will be referred to as Access RAM
High and Access RAM Low, respectively. Figure 4-7
indicates the Access RAM areas.
A bit in the instruction word specifies if the operation is
to occur in the bank specified by the BSR register or in
the Access Bank. This bit is denoted by the ‘a’ bit (for
access bit).
When forced in the Access Bank (a = 0), the last
address in Access RAM Low is followed by the first
address in Access RAM High. Access RAM High maps
the Special Function Registers, so that these registers
can be accessed without any software overhead. This is
useful for testing status flags and modifying control bits.
4.11
Bank Select Register (BSR)
The need for a large general purpose memory space
dictates a RAM banking scheme. The data memory is
partitioned into sixteen banks. When using direct
addressing, the BSR should be configured for the
desired bank.
BSR<3:0> holds the upper 4 bits of the 12-bit RAM
address. The BSR<7:4> bits will always read ‘0’s and
writes will have no effect.
A MOVLB instruction has been provided in the
instruction set to assist in selecting banks.
If the currently selected bank is not implemented, any
read will return all ‘0’s and all writes are ignored. The
Status register bits will be set/cleared as appropriate for
the instruction performed.
Each Bank extends up to FFh (256 bytes). All data
memory is implemented as static RAM.
A MOVFF instruction ignores the BSR, since the 12-bit
addresses are embedded into the instruction word.
Section 4.12 “Indirect Addressing, INDF and FSR
Registers” provides a description of indirect address-
ing, which allows linear addressing of the entire RAM
space.
FIGURE 4-8:
DIRECT ADDRESSING
Note 1:
For register file map detail, see Table 4-2.
2:
The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the
registers of the Access Bank.
3:
The MOVFF instruction embeds the entire 12-bit address in the instruction.
Data
Memory(1)
Direct Addressing
Bank Select(2)
Location Select(3)
BSR<3:0>
7
0
From Opcode(3)
00h
01h
0Eh
0Fh
Bank 0
Bank 1
Bank 14
Bank 15
1FFh
100h
0FFh
000h
EFFh
E00h
FFFh
F00h
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