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参数资料
型号： PIC18F8720T-E/PT
厂商： Microchip Technology
文件页数： 148/165页
文件大小： 0K
描述： IC PIC MCU FLASH 64KX16 80TQFP
标准包装： 1,200
系列： PIC® 18F
核心处理器： PIC
芯体尺寸： 8-位
速度： 25MHz
连通性： EBI/EMI，I²C，SPI，UART/USART
外围设备： 欠压检测/复位，LVD，POR，PWM，WDT
输入/输出数： 68
程序存储器容量： 128KB（64K x 16）
程序存储器类型： 闪存
EEPROM 大小： 1K x 8
RAM 容量： 3.75K x 8
电压 - 电源 (Vcc/Vdd)： 4.2 V ~ 5.5 V
数据转换器： A/D 16x10b
振荡器型： 外部
工作温度： -40°C ~ 125°C
封装/外壳： 80-TQFP
包装： 带卷 (TR)
配用： XLT80PT3-ND - SOCKET TRAN ICE 80MQFP/TQFP
AC164320-ND - MODULE SKT MPLAB PM3 80TQFP
AC174011-ND - MODULE SKT PROMATEII 80TQFP
2004 Microchip Technology Inc.
DS39609B-page 81
PIC18F6520/8520/6620/8620/6720/8720
7.3
Reading the Data EEPROM
Memory
To read a data memory location, the user must write the
address to the EEADRH:EEADR register pair, clear the
EEPGD control bit (EECON1<7>), clear the CFGS
control bit (EECON1<6>) and then set the RD control
bit (EECON1<0>). The data is available for the very
next instruction cycle; therefore, the EEDATA register
can be read by the next instruction. EEDATA will hold
this value until another read operation, or until it is
written to by the user (during a write operation).
EXAMPLE 7-1:
DATA EEPROM READ
7.4
Writing to the Data EEPROM
Memory
To write an EEPROM data location, the address must
first be written to the EEADRH:EEADR register pair
and the data written to the EEDATA register. Then the
sequence in Example 7-2 must be followed to initiate
the write cycle.
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. It is strongly
recommended that interrupts be disabled during this
code segment.
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code
execution (i.e., runaway programs). The WREN bit
should be kept clear at all times, except when updating
the
EEPROM.
The
WREN
bit
is
not
cleared
by hardware
After a write sequence has been initiated, EECON1,
EEADRH, EEADR and EEDATA cannot be modified.
The WR bit will be inhibited from being set unless the
WREN bit is set. Both WR and WREN cannot be set
with the same instruction.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EEPROM Write Complete
Interrupt Flag bit (EEIF) is set. The user may either
enable this interrupt, or poll this bit. EEIF must be
cleared by software.
EXAMPLE 7-2:
DATA EEPROM WRITE
MOVLW
DATA_EE_ADDRH
;
MOVWF
EEADRH
; Upper bits of Data Memory Address to read
MOVLW
DATA_EE_ADDR
;
MOVWF
EEADR
; Lower bits of Data Memory Address to read
BCF
EECON1, EEPGD
; Point to DATA memory
BCF
EECON1, CFGS
; Access EEPROM
BSF
EECON1, RD
; EEPROM Read
MOVF
EEDATA, W
; W = EEDATA
MOVLW
DATA_EE_ADDRH
;
MOVWF
EEADRH
; Upper bits of Data Memory Address to write
MOVLW
DATA_EE_ADDR
;
MOVWF
EEADR
; Lower bits of Data Memory Address to write
MOVLW
DATA_EE_DATA
;
MOVWF
EEDATA
; Data Memory Value to write
BCF
EECON1, EEPGD
; Point to DATA memory
BCF
EECON1, CFGS
; Access EEPROM
BSF
EECON1, WREN
; Enable writes
BCF
INTCON, GIE
; Disable Interrupts
MOVLW
55h
;
Required
MOVWF
EECON2
; Write 55h
Sequence
MOVLW
AAh
;
MOVWF
EECON2
; Write AAh
BSF
EECON1, WR
; Set WR bit to begin write
BSF
INTCON, GIE
; Enable Interrupts
; User code execution
BCF
EECON1, WREN
; Disable writes on write complete (EEIF set)
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