参数资料
型号: PIC18LF2420T-I/SO
厂商: Microchip Technology
文件页数: 27/151页
文件大小: 0K
描述: IC MCU FLASH 8KX16 28SOIC
产品培训模块: Asynchronous Stimulus
标准包装: 1,600
系列: PIC® 18F
核心处理器: PIC
芯体尺寸: 8-位
速度: 40MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,HLVD,POR,PWM,WDT
输入/输出数: 25
程序存储器容量: 16KB(8K x 16)
程序存储器类型: 闪存
EEPROM 大小: 256 x 8
RAM 容量: 768 x 8
电压 - 电源 (Vcc/Vdd): 2 V ~ 5.5 V
数据转换器: A/D 10x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
包装: 带卷 (TR)
2011-2012 Microchip Technology Inc.
Preliminary
DS41579C-page 295
PIC16(L)F1782/3
26.5.8
GENERAL CALL ADDRESS SUPPORT
The addressing procedure for the I2C bus is such that
the first byte after the Start condition usually deter-
mines which device will be the slave addressed by the
master device. The exception is the general call
address which can address all devices. When this
address is used, all devices should, in theory, respond
with an acknowledge.
The general call address is a reserved address in the
I2C protocol, defined as address 0x00. When the
GCEN bit of the SSPCON2 register is set, the slave
module will automatically ACK the reception of this
address regardless of the value stored in SSPADD.
After the slave clocks in an address of all zeros with
the R/W bit clear, an interrupt is generated and slave
software
can
read
SSPBUF
and
respond.
shows
a
general
call
reception
sequence.
In 10-bit Address mode, the UA bit will not be set on
the reception of the general call address. The slave
will prepare to receive the second byte as data, just as
it would in 7-bit mode.
If the AHEN bit of the SSPCON3 register is set, just as
with any other address reception, the slave hardware
will stretch the clock after the 8th falling edge of SCL.
The slave must then set its ACKDT value and release
the clock with communication progressing as it would
normally.
FIGURE 26-24:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
26.5.9
SSP MASK REGISTER
An SSP Mask (SSPMSK) register (Register 26-5) is
available in I2C Slave mode as a mask for the value
held in the SSPSR register during an address
comparison operation. A zero (‘0’) bit in the SSPMSK
register has the effect of making the corresponding bit
of the received address a “don’t care”.
This register is reset to all ‘1’s upon any Reset
condition and, therefore, has no effect on standard
SSP operation until written with a mask value.
The SSP Mask register is active during:
7-bit Address mode: address compare of A<7:1>.
10-bit Address mode: address compare of A<7:0>
only. The SSP mask has no effect during the
reception of the first (high) byte of the address.
SDA
SCL
S
SSPIF
BF (SSPSTAT<0>)
Cleared by software
SSPBUF is read
R/W = 0
ACK
General Call Address
Address is compared to General Call Address
Receiving Data
ACK
12
3
4
5
6
7
8
9
1
2
3
45
67
8
9
D7
D6
D5
D4
D3
D2
D1
D0
after ACK, set interrupt
GCEN (SSPCON2<7>)
’1’
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