参数资料
型号: PIC18LF2523-I/SP
厂商: Microchip Technology
文件页数: 22/54页
文件大小: 0K
描述: IC PIC MCU FLASH 16KX16 28-DIP
产品培训模块: Asynchronous Stimulus
标准包装: 15
系列: PIC® 18F
核心处理器: PIC
芯体尺寸: 8-位
速度: 40MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,HLVD,POR,PWM,WDT
输入/输出数: 25
程序存储器容量: 32KB(16K x 16)
程序存储器类型: 闪存
EEPROM 大小: 256 x 8
RAM 容量: 1.5K x 8
电压 - 电源 (Vcc/Vdd): 2 V ~ 5.5 V
数据转换器: A/D 10x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 28-DIP(0.300",7.62mm)
包装: 管件
产品目录页面: 643 (CN2011-ZH PDF)
2009 Microchip Technology Inc.
DS39755C-page 29
PIC18F2423/2523/4423/4523
The value in the ADRESH:ADRESL registers is
unknown following POR and BOR Resets and is not
affected by any other Reset.
After the A/D module has been configured as desired,
the selected channel must be acquired before the
conversion is started. The analog input channels must
have their corresponding TRIS bits selected as inputs.
To determine acquisition time, see Section 2.1 “A/D
After this acquisition time has elapsed, the A/D conver-
sion can be started. An acquisition time can be
programmed to occur between setting the GO/DONE
bit and the actual start of the conversion.
The following steps should be followed to perform an A/D
conversion:
1.
Configure the A/D module:
Configure analog pins, voltage reference and
digital I/O (ADCON1)
Select A/D input channel (ADCON0)
Select A/D acquisition time (ADCON2)
Select A/D conversion clock (ADCON2)
Turn on the A/D module (ADCON0)
2.
Configure the A/D interrupt (if desired):
Clear ADIF bit
Set ADIE bit
Set GIE bit
3.
Wait the required acquisition time (if required).
4.
Start conversion by setting the GO/DONE bit
(ADCON0<1>).
5.
Wait for the A/D conversion to complete by either:
Polling for the GO/DONE bit to be cleared
OR
Waiting for the A/D interrupt
6.
Read the A/D Result registers (ADRESH:ADRESL)
and clear the ADIF bit, if required.
7.
For the next conversion, go to step 1 or step 2,
as required.
The A/D conversion time per bit is defined as
TAD. A minimum wait of 2 TAD is required before
the next acquisition starts.
FIGURE 2-2:
A/D TRANSFER FUNCTION
FIGURE 2-3:
ANALOG INPUT MODEL
Dig
ita
lCo
d
eO
utp
ut
FFEh
003h
002h
001h
000h
0
.5
LS
B
1LS
B
1
.5
LS
B
2LS
B
2
.5
LS
B
40
94
LS
B
4
094
.5
LS
B
3LS
B
Analog Input Voltage
FFFh
40
95
LS
B
4
095
.5
LS
B
VAIN
CPIN
Rs
ANx
5 pF
VT = 0.6V
ILEAKAGE
RIC
≤ 1k
Sampling
Switch
SS
RSS
CHOLD = 25 pF
VSS
VDD
±100 nA
Legend: CPIN
VT
ILEAKAGE
RIC
SS
CHOLD
= Input Capacitance
= Threshold Voltage
= Leakage Current at the pin due to
= Interconnect Resistance
= Sampling Switch
= Sample/Hold Capacitance (from DAC)
various junctions
= Sampling Switch Resistance
RSS
VDD
6V
Sampling Switch
5V
4V
3V
2V
12
3
4
(k
Ω)
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