2010 Microchip Technology Inc.
Preliminary
DS39964B-page 95
PIC18F47J53 FAMILY
FDCh
PREINC2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
N/A
FDBh
PLUSW2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
N/A
FDAh
FSR2H
—
Indirect Data Memory Address Pointer 2 High Byte
---- xxxx
FD9h
FSR2L
Indirect Data Memory Address Pointer 2 Low Byte
xxxx xxxx
FD8h
STATUS
—
—N
OV
Z
DC
C
---x xxxx
FD7h
TMR0H
Timer0 Register High Byte
0000 0000
FD6h
TMR0L
Timer0 Register Low Byte
xxxx xxxx
FD5h
T0CON
TMR0ON
T08BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0
1111 1111
FD3h
OSCCON
IDLEN
IRCF2
IRCF1
IRCF0
OSTS
FLTS
SCS1
SCS0
0110 q000
FD2h
CM1CON
CON
COE
CPOL
EVPOL1
EVPOL0
CREF
CCH1
CCH0
0001 1111
FD1h
CM2CON
CON
COE
CPOL
EVPOL1
EVPOL0
CREF
CCH1
CCH0
0001 1111
FD0h
RCON
IPEN
—CM
RI
TO
PD
POR
BOR
0-11 11qq
FCFh
TMR1H
Timer1 Register High Byte
xxxx xxxx
FCEh
TMR1L
Timer1 Register Low Bytes
xxxx xxxx
FCDh
T1CON
TMR1CS1
TMR1CS0
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
RD16
TMR1ON
0000 0000
FCCh
TMR2
Timer2 Register
0000 0000
FCBh
PR2
Timer2 Period Register
1111 1111
FCAh
T2CON
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0
TMR2ON
T2CKPS1
T2CKPS0
-000 0000
FC9h
SSP1BUF
MSSP1 Receive Buffer/Transmit Register
xxxx xxxx
FC8h
SSP1ADD
MSSP1 Address Register (I2C Slave Mode). MSSP1 Baud Rate Reload Register (I2C Master Mode).
0000 0000
FC8h
SSP1MSK
MSK7
MSK6
MSK5
MSK4
MSK3
MSK2
MSK1
MSK0
---- ----
FC7h
SSP1STAT
SMP
CKE
D/A
PS
R/W
UA
BF
1111 1111
FC6h
SSP1CON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000
FC5h
SSP1CON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
0000 0000
FC5h
SSP1CON2
GCEN
ACKSTAT
ADMSK5
ADMSK4
ADMSK3
ADMSK2
ADMSK1
SEN
0000 0000
FC4h
ADRESH
A/D Result Register High Byte
xxxx xxxx
FC3h
ADRESL
A/D Result Register Low Byte
xxxx xxxx
FC2h
ADCON0
VCFG1
VCFG0
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
0000 0000
FC1h
ADCON1
ADFM
ADCAL
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
0000 0000
FC0h
WDTCON
REGSLP
LVDSTAT
ULPLVL
VBGOE
DS
ULPEN
ULPSINK
SWDTEN
1xx0 0000
FBFh
PSTR1CON
CMPL1
CMPL0
—
STRSYNC
STRD
STRC
STRB
STRA
00-0 0001
FBEh
ECCP1AS
ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0
PSS1AC1
PSS1AC0
PSS1BD1
PSS1BD0
0000 0000
FBDh
ECCP1DEL
P1RSEN
P1DC6
P1DC5
P1DC4
P1DC3
P1DC2
P1DC1
P1DC0
0000 0000
FBCh
CCPR1H
Capture/Compare/PWM Register 1 High Byte
xxxx xxxx
FBBh
CCPR1L
Capture/Compare/PWM Register 1 Low Byte
xxxx xxxx
FBAh
CCP1CON
P1M1
P1M0
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
0000 0000
FB9h
PSTR2CON
CMPL1
CMPL0
—
STRSYNC
STRD
STRC
STRB
STRA
00-0 0001
FB8h
ECCP2AS
ECCP2ASE ECCP2AS2 ECCP2AS1 ECCP2AS0
PSS2AC1
PSS2AC0
PSS2BD1
PSS2BD0
0000 0000
FB7h
ECCP2DEL
P2RSEN
P2DC6
P2DC5
P2DC4
P2DC3
P2DC2
P2DC1
P2DC0
0000 0000
FB6h
CCPR2H
Capture/Compare/PWM Register 2 High Byte
xxxx xxxx
FB5h
CCPR2L
Capture/Compare/PWM Register 2 Low Byte
xxxx xxxx
FB4h
CCP2CON
P2M1
P2M0
DC2B1
DC2B0
CCP2M3
CCP2M2
CCP2M1
CCP2M0
0000 0000
FB3h
CTMUCONH
CTMUEN
—
CTMUSIDL
TGEN
EDGEN
EDGSEQEN
IDISSEN
CTTRIG
0-00 0000
FB2h
CTMUCONL
EDG2POL
EDG2SEL1 EDG2SEL0
EDG1POL
EDG1SEL1 EDG1SEL0
EDG2STAT
EDG1STAT 0000 00xx
FB1h
CTMUICON
ITRIM5
ITRIM4
ITRIM3
ITRIM2
ITRIM1
ITRIM0
IRNG1
IRNG0
0000 0000
FB0h
SPBRG1
EUSART1 Baud Rate Generator Register Low Byte
0000 0000
FAFh
RCREG1
EUSART1 Receive Register
0000 0000
TABLE 6-4:
REGISTER FILE SUMMARY (PIC18F47J53 FAMILY) (CONTINUED)
Addr.
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Legend:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify
Note 1:
Implemented only for 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53).
2:
Implemented only for 28-pin devices (PIC18F26J53, PIC18F27J53, PIC18LF26J53 and PIC18LF27J53).
3:
Implemented only for devices with 128 Kbyte of program memory (PIC18F27J53, PIC18F47J53, PIC18LF27J53 and PIC18LF47J53).