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| 型号： | PIC18LF47J13-I/ML |
| 厂商： | Microchip Technology |
| 文件页数： | 36/71页 |
| 文件大小： | 0K |
| 描述： | IC PIC MCU 128KB FLASH 44QFN |
| 产品培训模块： | 8-bit PIC® Microcontroller Portfolio |
| 标准包装： | 45 |
| 系列： | PIC® XLP™ 18F |
| 核心处理器： | PIC |
| 芯体尺寸： | 8-位 |
| 速度： | 48MHz |
| 连通性： | I²C，LIN，SPI，UART/USART |
| 外围设备： | 欠压检测/复位，POR，PWM，WDT |
| 输入/输出数： | 34 |
| 程序存储器容量： | 128KB（64K x 16） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 3.8K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2 V ~ 2.75 V |
| 数据转换器： | A/D 13x10b/12b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 44-VQFN 裸露焊盘 |
| 包装： | 管件 |
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2010-2012 Microchip Technology Inc.
DS41412E-page 41
PIC18(L)F2X/4XK22
TABLE 2-3:
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
2.11
Clock Switching
The system clock source can be switched between
external and internal clock sources via software using
the System Clock Select (SCS<1:0>) bits of the
OSCCON register.
PIC18(L)F2X/4XK22 devices contain circuitry to pre-
vent clock “glitches” when switching between clock
sources. A short pause in the device clock occurs dur-
ing the clock switch. The length of this pause is the sum
of two cycles of the old clock source and three to four
cycles of the new clock source. This formula assumes
that the new clock source is stable.
Clock transitions are discussed in greater detail in
2.11.1
SYSTEM CLOCK SELECT
(SCS<1:0>) BITS
The System Clock Select (SCS<1:0>) bits of the
OSCCON register select the system clock source that
is used for the CPU and peripherals.
When SCS<1:0> = 00, the system clock source is
determined by configuration of the FOSC<3:0>
bits in the CONFIG1H Configuration register.
When SCS<1:0> = 10, the system clock source is
chosen by the internal oscillator frequency
selected by the INTSRC bit of the OSCTUNE
register, the MFIOSEL bit of the OSCCON2
register and the IRCF<2:0> bits of the OSCCON
register.
When SCS<1:0> = 01, the system clock source is
the 32.768 kHz secondary oscillator shared with
Timer1, Timer3 and Timer5.
After a Reset, the SCS<1:0> bits of the OSCCON
register are always cleared.
2.11.2
OSCILLATOR START-UP TIME-OUT
STATUS (OSTS) BIT
The Oscillator Start-up Time-out Status (OSTS) bit of
the OSCCON register indicates whether the system
clock is running from the external clock source, as
defined by the FOSC<3:0> bits in the CONFIG1H
Configuration register, or from the internal clock
source. In particular, when the primary oscillator is the
source of the primary clock, OSTS indicates that the
Oscillator Start-up Timer (OST) has timed out for LP,
XT or HS modes.
OSC Mode
OSC1 Pin
OSC2 Pin
RC, INTOSC with CLKOUT Floating, external resistor should pull high
At logic low (clock/4 output)
RC with IO
Floating, external resistor should pull high
Configured as PORTA, bit 6
INTOSC with IO
Configured as PORTA, bit 7
Configured as PORTA, bit 6
EC with IO
Floating, pulled by external clock
Configured as PORTA, bit 6
EC with CLKOUT
Floating, pulled by external clock
At logic low (clock/4 output)
LP, XT, HS
Feedback inverter disabled at quiescent
voltage level
Feedback inverter disabled at quiescent
voltage level
Note:
See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset.
Note:
Any automatic clock switch, which may
occur from Two-Speed Start-up or Fail-
Safe Clock Monitor, does not update the
SCS<1:0> bits of the OSCCON register.
The user can monitor the SOSCRUN,
MFIOFS
and
LFIOFS
bits
of
the
OSCCON2 register, and the HFIOFS and
OSTS bits of the OSCCON register to
determine the current system clock source.
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