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参数资料
型号： PIC18LF6520T-I/PTG
厂商： Microchip Technology
文件页数： 154/165页
文件大小： 0K
描述： IC MCU FLASH 16KX16 64TQFP
标准包装： 1,200
系列： PIC® 18F
核心处理器： PIC
芯体尺寸： 8-位
速度： 40MHz
连通性： I²C，SPI，UART/USART
外围设备： 欠压检测/复位，LVD，POR，PWM，WDT
输入/输出数： 52
程序存储器容量： 32KB（16K x 16）
程序存储器类型： 闪存
EEPROM 大小： 1K x 8
RAM 容量： 2K x 8
电压 - 电源 (Vcc/Vdd)： 2 V ~ 5.5 V
数据转换器： A/D 12x10b
振荡器型： 内部
工作温度： -40°C ~ 85°C
封装/外壳： 64-TQFP
包装： 带卷 (TR)
其它名称： PIC18LF6520T-IPTG
2004 Microchip Technology Inc.
DS39609B-page 87
PIC18F6520/8520/6620/8620/6720/8720
9.0
INTERRUPTS
The PIC18FXX20 devices have multiple interrupt
sources and an interrupt priority feature that allows
each interrupt source to be assigned a high or a low
priority level. The high priority interrupt vector is at
000008h, while the low priority interrupt vector is at
000018h. High priority interrupt events will override any
low priority interrupts that may be in progress.
There are thirteen registers which are used to control
interrupt operation. They are:
RCON
INTCON
INTCON2
INTCON3
PIR1, PIR2, PIR3
PIE1, PIE2, PIE3
IPR1, IPR2, IPR3
It is recommended that the Microchip header files,
supplied with MPLAB IDE, be used for the symbolic bit
names in these registers. This allows the assembler/
compiler to automatically take care of the placement of
these bits within the specified register.
Each interrupt source has three bits to control its
operation. The functions of these bits are:
Flag bit to indicate that an interrupt event
occurred
Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
Priority bit to select high priority or low priority
The interrupt priority feature is enabled by setting the
IPEN bit (RCON<7>). When interrupt priority is
enabled, there are two bits which enable interrupts
globally. Setting the GIEH bit (INTCON<7>) enables all
interrupts that have the priority bit set. Setting the GIEL
bit (INTCON<6>) enables all interrupts that have the
priority bit cleared. When the interrupt flag, enable bit
and appropriate global interrupt enable bit are set, the
interrupt will vector immediately to address 000008h or
000018h, depending on the priority level. Individual
interrupts can be disabled through their corresponding
enable bits.
When the IPEN bit is cleared (default state), the
interrupt priority feature is disabled and interrupts are
compatible with PICmicro mid-range devices. In Com-
patibility mode, the interrupt priority bits for each source
have no effect. INTCON<6> is the PEIE bit, which
enables/disables
all peripheral interrupt sources.
INTCON<7> is the GIE bit, which enables/disables all
interrupt sources. All interrupts branch to address
000008h in Compatibility mode.
When an interrupt is responded to, the Global Interrupt
Enable bit is cleared to disable further interrupts. If the
IPEN bit is cleared, this is the GIE bit. If interrupt priority
levels are used, this will be either the GIEH or GIEL bit.
High priority interrupt sources can interrupt a low
priority interrupt.
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address
(000008h or 000018h). Once in the Interrupt Service
Routine, the source(s) of the interrupt can be deter-
mined by polling the interrupt flag bits. The interrupt
flag bits must be cleared in software before re-enabling
interrupts to avoid recursive interrupts.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine and sets the GIE bit (GIEH or GIEL
if priority levels are used), which re-enables interrupts.
For external interrupt events, such as the INT pins or
the PORTB input change interrupt, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one or two-cycle instructions.
Individual interrupt flag bits are set, regardless of the
status of their corresponding enable bit or the GIE bit.
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