参数资料
型号: PIC32MX664F128LT-I/BG
厂商: Microchip Technology
文件页数: 10/12页
文件大小: 0K
描述: IC PIC MCU 128KBIT FLASH 121XBGA
标准包装: 2,200
系列: PIC® 32MX
核心处理器: MIPS32? M4K?
芯体尺寸: 32-位
速度: 80MHz
连通性: 以太网,I²C,SPI,UART/USART,USB OTG
外围设备: 欠压检测/复位,DMA,POR,PWM,WDT
程序存储器容量: 128KB(128K x 8)
程序存储器类型: 闪存
RAM 容量: 32K x 8
电压 - 电源 (Vcc/Vdd): 2.3 V ~ 3.6 V
数据转换器: A/D 16x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 121-TFBGA
包装: 带卷 (TR)
2010-2012 Microchip Technology Inc.
DS80511G-page 7
PIC32MX534/564/664/764
18. Module: I2C
The slave address, 0x78, is one of a group of
reserved addresses. It is used as the upper byte of
a 10-bit address when 10-bit addressing is
enabled. The I2C module control register allows
the programmer to enable both 10-bit addressing
and strict enforcement of reserved addressing,
with the A10M and STRICT bits, respectively.
When both bits are cleared, the device should
respond to the reserved address 0x78, but it does
not.
Work around
None.
Affected Silicon Revisions
19. Module: USB
If the bus has been idle for more than 3 ms, the
UIDLE interrupt flag is set. If software clears the
interrupt flag, and the bus remains idle, the UIDLE
interrupt flag will not be set again.
Work around
Software can leave the UIDLE bit set until it has
received some indication of bus resumption.
(Resume, Reset, SOF, or Error).
Affected Silicon Revisions
20. Module: CPU
When both prefetch and instruction cache are
enabled, a Data Bus Exception (DBE) may occur if
an interrupt is encountered by the CPU while it is
accessing constant data (not instructions) from
Flash memory.
Work around
To avoid a DBE, use one of the following two
solutions:
1.
Structure application code, such that inter-
rupts are not used while the CPU is accessing
data from Flash memory.
2.
Disable either the Prefetch module or CPU
cache functionality as follows (by default both
are disabled on a Power-on Reset (POR)):
a)
To disable the Prefetch module, set the
Predictive
Prefetch
Enable
bits,
PREFEN<1:0>, in the Cache Control
Register, CHECON<6:5>, to ‘00’.
b)
To disable CPU cache, set the Kseg0
bits, K0<2:0>, in the CP0 Configuration
Register, Config<2:0>, to ‘010’.
Affected Silicon Revisions
21. Module: CPU
During normal operation, if a CPU write operation
is interrupted by an incoming interrupt, it should be
aborted (not completed) and resumed after the
interrupt is serviced. However, some of these write
operations may not be aborted, resulting in a
double write to peripherals by the CPU (the first
write during the interrupt and the second write after
the interrupt is serviced).
Work around
Most peripherals are not affected by this issue, as
a double write will not have a negative impact.
However, the following communication peripherals
will double-send data if their respective transmit
buffers are written twice: SPI, I2C, UART and PMP.
To avoid double transmission of data, utilize DMA
to transfer data to these peripherals or disable
interrupts while writing to these peripherals.
Affected Silicon Revisions
A0
A1
A2
XX
X
Note:
Resume and Reset are the only interrupts
that should be following UIDLE assertion.
If the UIDLE bit is set, it should be okay to
suspend the USB module (as long as this
code is protected by the GUARD and/or
ACTPEND logic). This will require soft-
ware to clear the UIDLE interrupt enable
bit to exit the USB ISR (if using interrupt
driven code).
A0
A1
A2
XX
X
Note:
Disabling either the cache or Prefetch
module will have minimum performance
degradation, with a typical application
realizing 10 percent or less performance
impact.
A0
A1
A2
XX
X
A0
A1
A2
XX
X
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