参数资料
型号: PIC32MX664F128LT-I/BG
厂商: Microchip Technology
文件页数: 7/12页
文件大小: 0K
描述: IC PIC MCU 128KBIT FLASH 121XBGA
标准包装: 2,200
系列: PIC® 32MX
核心处理器: MIPS32? M4K?
芯体尺寸: 32-位
速度: 80MHz
连通性: 以太网,I²C,SPI,UART/USART,USB OTG
外围设备: 欠压检测/复位,DMA,POR,PWM,WDT
程序存储器容量: 128KB(128K x 8)
程序存储器类型: 闪存
RAM 容量: 32K x 8
电压 - 电源 (Vcc/Vdd): 2.3 V ~ 3.6 V
数据转换器: A/D 16x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 121-TFBGA
包装: 带卷 (TR)
PIC32MX534/564/664/764
DS80511G-page 4
2010-2012 Microchip Technology Inc.
Silicon Errata Issues
1.
Module: JTAG
On 64-pin devices, an external pull-up resistor is
required on the TMS pin for proper JTAG.
Work around
Connect a 100k-200k pull-up to the TMS pin.
Affected Silicon Revisions
2.
Module: CAN
When an abort request occurs concurrently with a
successful message transmission, and additional
messages remain in the FIFO, these remaining
messages are not transmitted and the TXBAT bit
does not reflect the abort.
Work around
The actual FIFO status can be determined by the
FIFO pointers CFIFOCI and CFIFOUA.
Affected Silicon Revisions
3.
Module: SPI
In Slave mode with Chip Select (CS) enabled, if
the Master deasserts CS before the SPI clock has
returned to the Idle state, the SPIBUSY bit will
remain set until the next SPI data transfer is
completed. The other SPI status bits will reflect the
actual status.
Work around
None.
Affected Silicon Revisions
4.
Module: SPI
In Slave mode when entering Sleep mode after a
SPI transfer with SPI interrupts enabled, a false
interrupt may be generated waking the device.
This interrupt can be cleared; however, entering
Sleep may cause the condition to occur again.
Work around
Do not use SPI in Slave mode as a wake-up
source from Sleep mode.
Affected Silicon Revisions
5.
Module: SPI
In Frame mode the module is not immediately
ready for further transfers after clearing the
SPITUR bit. The SPITUR bit will be cleared by
hardware before the SPI state machine is
prepared for the next operation.
Work around
Firmware must wait at least four bit times before
writing to the SPI registers after clearing the
SPITUR bit.
Affected Silicon Revisions
6.
Module: SPI
Byte writes to the SPISTAT register are not
decoded correctly. A byte write to byte zero of
SPISTAT is actually performed on both byte zero
and byte one. A byte write to byte one of SPISTAT
is ignored.
Work around
Only perform word operations on the SPISTAT
register.
Affected Silicon Revisions
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A2).
A0
A1
A2
XX
X
A0
A1
A2
XX
X
A0
A1
A2
XX
X
A0
A1
A2
XX
X
A0
A1
A2
XX
X
A0
A1
A2
XX
X
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