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参数资料
| 型号： | PIIPM25P12B008X |
| 厂商： | Vishay Semiconductors |
| 文件页数： | 3/28页 |
| 文件大小： | 0K |
| 描述： | IC PWR MODULE PROG ISO 25A 1200V |
| 标准包装： | 1 |
| 模块/板类型： | 编程器模块 |
| 适用于相关产品： | 伺服电机 |
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PIIPM25P12B008
I27147 02 - Oct
Signal pins on RS422 serial port
Symbol
Vin iso
GND iso
Tx+
Tx-
Rx+
Lead Description
External 5V supply voltage for opto-couplers and line driver supply
Extenal 5V supply ground reference for opto-couplers and line driver supply
RS422 Trasmitter Non inverting Driver Output
RS422 Trasmitter Inverting Driver Output
RS422 Receiver Non inverting Driver Input,
Pin number
6
7
1
2
4
Rx-
Enc1 – Hall1 / SpiCK
Enc2 – Hall2 / SpiSTE
Strb – Hall3 / SpiRx
SpiTx
Vin
COM
RS422 Receiver Inverting Driver Input
Incremental Encoder 1 / Hall effect sensor input 1/ SpiCK input (GND iso referenced)
Incremental Encoder 2 / Hall effect sensor input 2 / SpiSTE input (GND iso referenced)
Incremental Encoder Strobe / Hall effect sensor input 3 / SpiRx input (GND iso ref.).
Also used for DSP boot feature using DSP boot ROM. Please see note below.
SpiTx output (GND iso referenced)
External 15V supply voltage. Internally referred to DC bus minus pin (DC -)
External 15V supply ground reference. This pin is directly connected to DC -
3
5
9
10
8
17-18
19-20
RS422
serial
port
Signal pins on IEEE1149.1 JTAG connector
CAUTION DO NOT APPLY DC BUS VOLTAGE WHEN JTAG INTERFACE IS CONNECTED, SEVERE
DAMAGE WILL OCCUR ON POWER MODULE AND ON YOUR EQUIPMENT!
Symbol
TMS
TMS2
TDI
TDO
TCK
Lead Description
JTAG test mode select
JTAG test mode select 2
JTAG test data input
JTAG test data output
JTAG test clock. TCK is a 10MHz clock source from the emulation pod.
This signal can be used to drive the system test clock.
State
Input
Input
Input
Output
Input
Pin number
12
5-6
14
13
15
TRST~ JTAG test reset
Input
11
EMU0 Emulation pin 0
EMU1/OFF~ Emulation pin 1
Presence detect.
PD Indicates that the emulation cable is connected and that the PI-IPM log ic is
powered up. PD is tied to the DSP 3.3V supply through a 1k resistor.
I/O
I/O
Output
9-10
7-8
1
IEEE1149.1
JTAG
see note below.
TCK_RET
Boot-En~
JTAG test clock return. Test clock input to the emulator.
Internally short circuited to TCK.
Boot ROM enable. This pin is sampled during DSP reset, pulling it low
enables DSP boot ROM (Flash version only). 47k internal pull-up. Please
1
Output
Input
16
17
COM Exernal 15V supply ground reference. This pin is directly connected to DC-
~ indicates active low signals
1
To enable DSP boot ROM for boot load feature through SCI at 40Mhz clock operation follow these steps:
1) Connect Boot-En~ to COM;
2) Connect STR – Hall3 / SpiRx to GND iso;
3) Apply voltage to Vin iso;
4) Apply-voltage to Vin (after Vin iso to allow proper configuration).
www.irf.com
N/A
20
3
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