参数资料
型号: PK30N512VLL100
厂商: Freescale Semiconductor
文件页数: 20/66页
文件大小: 0K
描述: IC ARM CORTEX MCU 512K 100-LQFP
产品培训模块: Kinetis® Cortex-M4 Microcontroller Family
标准包装: 1
系列: Kinetis
核心处理器: ARM? Cortex?-M4
芯体尺寸: 32-位
速度: 100MHz
连通性: CAN,I²C,IrDA,SDHC,SPI,UART/USART
外围设备: DMA,I²S,LCD,LVD,POR,PWM,WDT
输入/输出数: 66
程序存储器容量: 512KB(512K x 8)
程序存储器类型: 闪存
RAM 容量: 128K x 8
电压 - 电源 (Vcc/Vdd): 1.71 V ~ 3.6 V
数据转换器: A/D 30x16b,D/A 1x12b
振荡器型: 内部
工作温度: -40°C ~ 105°C
封装/外壳: 100-LQFP
包装: 托盘
Table 15. MCG specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
PLL
fvco
VCO operating frequency
48.0
100
MHz
Ipll
PLL operating current
PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 48)
1060
A
Ipll
PLL operating current
PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 24)
600
A
fpll_ref
PLL reference frequency range
2.0
4.0
MHz
Jcyc_pll
PLL period jitter (RMS)
fvco = 48 MHz
fvco = 100 MHz
120
50
ps
Jacc_pll
PLL accumulated jitter over 1s (RMS)
fvco = 48 MHz
fvco = 100 MHz
1350
600
ps
Dlock
Lock entry frequency tolerance
± 1.49
± 2.98
%
Dunl
Lock exit frequency tolerance
± 4.47
± 5.97
%
tpll_lock
Lock detector detection time
150 × 10-6
+ 1075(1/
fpll_ref)
s
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation
(
Δfdco_t) over voltage and temperature should be considered.
4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
6. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
7. Excludes any oscillator currents that are also consuming power while PLL is in operation.
8. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
9. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
6.3.2 Oscillator electrical specifications
This section provides the electrical characteristics of the module.
Peripheral operating requirements and behaviors
K30 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
27
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