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参数资料
| 型号： | PLL1706 |
| 英文描述： | RS232/EIA562/RS485 Transceivers; Package: PDIP; No of Pins: 24; Temperature Range: -40°C to +85°C |
| 中文描述： | 3.3伏双PLL的多时钟发生器 |
| 文件页数： | 3/17页 |
| 文件大小： | 128K |
| 代理商： | PLL1706 |
PLL1705
PLL1706
SLES046A
–
AUGUST 2002
–
REVISED SEPTEMBER 2002
www.ti.com
3
ELECTRICAL CHARACTERISTICS
all specifications at TA = 25
°
C, VDD1
–
VDD3 (= VDD) = VCC = 3.3 V, fM = 27 MHz, crystal oscillation, fS = 48 kHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DIGITAL INPUT/OUTPUT
Logic input
VIH (1)
Inputlogiclevel
VIL (1)
IIH (1)
Inputlogiccurrent
IIL (1)
VIN = 0 V
Logic output
VOH (2)
Outputlogiclevel
VOL (2)
IOL = 4 mA
Standard fS
Sampling requency
Double fS
MASTER CLOCK (MCKO1, 2) CHARACTERISTICS
(fM = 27 MHz, C1 = C2 = 15 pF, CL = 20 pF on measurement pin)
Master clock frequency
VIH
Inputlevel(3)
VIL
IIH
Inputcurrent(3)
IIL
VIN = 0 V
Output voltage (4)
Output rise time
20% to 80% of VDD
Output fall time
80% to 20% of VDD
For crystal oscillation
For external clock
Clock jitter (5)
Power-up time (6)
PLL AC CHARACTERISTICS (SCKO0
–
3)
(fM = 27 MHz, CL = 20 pF on measurement pin)
SCKO0
Fixed
SCKO1
SCKO2
256 fS
SCKO3
384 fS
Output rise time
20% to 80% of VDD
Output fall time
80% to 20% of VDD
Output duty cycle
Output clock jitter (5)
PLL1705, to stated output frequency
Frequency Settling Time(7)
PLL1706, to stated output frequency
Power-up time (8)
To stated output frequency
MIN
TYP
MAX
UNIT
CMOS compatible
0.7VDD
3.6
Vdc
Input logic level
0.3 VDD
VIN = VDD
65
100
±
10
μ
A
Input logic current
CMOS
VDD
–
0.4 V
IOH =
–
4 mA
Vdc
Vdc
Output logic level
0.4
48
96
Samplingfrequency
32
64
44.1
88.2
kHz
26.73
27
27.27
MHz
0.7 VCC
V
Input level(3)
0.3 VCC
VIN = VCC
±
10
±
10
μ
A
Input current(3)
3.5
2.0
2.0
48%
50%
50
0.5
Vp-p
ns
ns
Duty cycle
45%
55%
ps
ms
1.5
33.8688
Selectable for 44.1 kHz
16.9344
8.192
12.288
33.8688
24.576
36.864
MHz
Output system clock frequency
12.288
18.432
2.0
2.0
50
50
50
80
ns
ns
%
ps
ns
ns
ms
45
55
100
150
200
FrequencySettlingTime(7)
3
6
(1)Pins 5, 6, 7, 12: FS1/MD, FS2/MC, SR/ML, CSEL (Schmitt-trigger input with internal pulldown, 3.3-V tolerant)
(2)Pins 2, 3, 14, 15, 18, 19: SCKO2, SCKO3, MCKO1, MCKO2, SCKO1, SCKO0
(3)Pin 10: XT1
(4)Pin 11: XT2
(5)Jitter performance is specified as standard deviation of jitter for 27-MHz crystal oscillation and default SCKO frequency setting. Jitter
performance varies with master clock mode, SCKO frequency setting and load capacitance on each clock output.
(6)The delay time from power on to oscillation
(7)The settling time when the sampling frequency is changed
(8)The delay time from power on to lockup
(9)fM = 27-MHz crystal oscillation, no load on MCKO1, MCKO2, SCKO0, SCKO1, SCKO2, SCKO3. Power supply current varies with sampling
frequency selection and load condition.
(10)While all bits of CE[6:1] are 0, the PLL1706 goes into power-down mode.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PLL1706DBQ | 功能描述:时钟发生器及支持产品 3.3 V Dual PLL Multi Clock Gen RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| PLL1706DBQG4 | 功能描述:时钟发生器及支持产品 3.3V Dual PLL Multi- Clock Gen RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| PLL1706DBQR | 功能描述:时钟发生器及支持产品 3.3V Dual PLL Multi- Clock Gen RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| PLL1706DBQRG4 | 功能描述:时钟发生器及支持产品 3.3V Dual PLL Multi- Clock Gen RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| PLL1707 | 制造商:BB 制造商全称:BB 功能描述:3.3 V DUAL PLL MULTICLOCK GENERATOR |
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