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参数资料
| 型号： | PLRXPL-VE-SH4-23-N |
| 厂商： | JDS UNIPHASE CORP |
| 元件分类： | 光收发 |
| 英文描述： | FIBER OPTIC TRANSCEIVER, 840-860nm, 9000Mbps(Tx), 9000Mbps(Rx), SURFACE MOUNT, LC CONNECTOR |
| 封装： | ROHS COMPLIANT PACKAGE |
| 文件页数： | 17/22页 |
| 文件大小： | 543K |
| 代理商： | PLRXPL-VE-SH4-23-N |
4
8.5 G SFP+ 850 NM LIMITING TRANSCEIVER,
8 GIGABIT FIBRE CHANNEL COMPLIANT
Figure 2
Recommended application schematic for the 8 G SFP+ optical transceiver
Notes
Power supply ltering components should be placed as close to the Vcc pins of the host connector as possible for optimal performance.
PECL driver and receiver components will require biasing networks. Please consult application notes from suppliers of these components. CML I/O on the PHY are sup-
ported. Good impedance matching for the driver and receiver is required.
SDA and SCL should be bi-directional open collector connections in order to implement serial ID in JDSU SFP+ transceiver modules.
R1/R2 and R3/R4 are normally included in the output and input of the PHY. Please check the application notes for the IC in use.
* Transmission lines should be 100 Ω differential traces. Vias and other transmission line discontinuities should be avoided. In order to meet the host TP1 output jitter and
TP4 jitter tolerance requirements it is recommended that the PHY has both transmitter pre-emphasis to equalize the transmitter traces and receiver equalization to equalize the
receiver traces. With appropriate transmitter pre-emphasis and receiver equalization, up to 8 dB of loss at 5 GHz can be tolerated.
** R5 and R6 are required when an Open Collector driver is used in place of CMOS or TTL drivers. 5 kΩ value is appropriate.
*** The value of Rp and Rq depend on the capacitive loading of these lines and the two wire interface clock frequency. See SFF-8431. A value of 10 kΩ is appropriate for 80 pF
capacitive loading at 100 kHz clock frequency.
Receiver (Tx Fault)
Vcc
10 k
Ω
CMOS, TTL, or
Open Collector Driver
(Tx Disable)
Open Collector
Bidirectional
SDA
Vcc
Rp***
Vcc
Open Collector
Bidirectional
SCL
Rq
***
Mod_ABS
10 k
Ω
Vcc
1 VeeT
2 Tx Fault
3 Tx Disable
4 SDA
5 SCL
6 MOD_ABS
7 RS0
8 LOS
9 RS1
10 VeeR
VeeT 20
TD- 19
TD+ 18
VeeT 17
VccT 16
VccR 15
VeeR 14
RD+ 13
RD-
12
VeeR 11
10 k
Ω
Vcc
Receiver (LOS)
R1
* 50 Ω
R2
* 50 Ω
L1
L2
Z
* = 100Ω
PECL Driver
(TX DATA)
C1
C2
C5
C4
C3
CMOS or TTL Driver
(RS0 Rx Rate Select)
CMOS or TTL Driver
(RS1 Tx Rate Select)
Vcc
R6
R5
Vcc
Vcc +3.3V
Input
R3
*
50
Ω
R4
*
50
Ω
PECL Receiver
(RX DATA)
Z
* = 100 Ω
Power Supply Filter
C6
Ry
Rx
Section 2
Application Schematic
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