![](http://datasheet.mmic.net.cn/330000/PM4318_datasheet_16444259/PM4318_24.png)
PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
15
Pin Name
Type
Pin
No.
Function
AC1FP/TDN[2]
Input
Y22
The SBI ADD bus C1 octet frame pulse signal (AC1FP) provides
frame synchronisation for devices connected via an SBI interface.
AC1FP must be asserted for 1 REFCLK cycle every 500 μs or
multiples thereof (i.e. every 9720 n REFCLK cycles, where n is a
positive integer). All devices connected to the SBI ADD bus must
be synchronised to a AC1FP signal from a single source.
AC1FP is sampled on the rising edge of REFCLK.
AC1FP shares the same pin as the TDN[2] input. AC1FP is
selected when SBI_EN or SBI2CLK is tied high.
DC1FP/TDN[3]
Input
AA21
The SBI DROP bus C1 octet frame pulse signal (DC1FP)
provides frame synchronisation for devices connected via an SBI
interface. DC1FP must be asserted for 1 REFCLK cycle every
500 μs or multiples thereof (i.e. every 9720 n REFCLK cycles,
where n is a positive integer). All devices connected to the SBI
DROP bus must be synchronised to a DC1FP signal from a single
source.
DC1FP is sampled on the rising edge of REFCLK.
DC1FP shares the same pin as the TDN[3] input. DC1FP is
selected when SBI_EN or SBI2CLK is tied high.
C1FPOUT/RDN/RLCV[3]
Output
W15
The C1 octet frame pulse output signal (C1FPOUT) may be used
to provide frame synchronisation for devices interconnected via
an SBI interface. C1FPOUT is asserted for 1 REFCLK cycle
every 500 μs (i.e. every 9720 REFCLK cycles). If C1FPOUT is
used for synchronisation, it must be connected to the A/DC1FP
inputs of all the devices connected to the SBI ADD or DROP bus.
C1FPOUT is updated on the rising edge of REFCLK.
C1FPOUT shares the same pin as the RDN/RLCV[3] output.
C1FPOUT is selected when SBI_EN or SBI2CLK is tied high.
ADATA[0]/TDP[1]
ADATA[1]/TDP[2]
ADATA[2]/TDP[3]
ADATA[3]/TDP[4]
ADATA[4]/TDP[5]
ADATA[5]/TDP[6]
ADATA[6]/TDP[7]
ADATA[7]/TDP[8]
Input
W22
V19
Y21
Y19
Y2
Y1
W1
U2
The SBI ADD bus data signals (ADATA[7:0]) contain time division
multiplexed transmit data from up to 84 independently timed links.
Link data is transported as T1 or E1 tributaries within the SBI
TDM bus structure. The OCTLIU may be configured to extract
data from up to 8 tributaries within the structure.
ADATA[7:0] are sampled on the rising edge of REFCLK.
ADATA[7:0] share the same pins as the TDP[8:1] inputs.
ADATA[7:0] are selected when SBI_EN or SBI2CLK is tied high.