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| 型号： | PM4325 |
| 厂商： | PMC-Sierra, Inc. |
| 英文描述： | Octal Short Haul T1/E1/J1 Low Latency Transport Line Interface |
| 中文描述： | 八路短途运输的T1/E1/J1低延迟线路接口 |
| 文件页数： | 1/2页 |
| 文件大小： | 58K |
| 代理商： | PM4325 |
PM4325
OCTLIU ST
Octal Short Haul T1/E1/J1 Low Latency Transport Line Interface
PMC-2030527 (R2)
PROPRIETARY AND CONFIDENTIAL TO PMC
-
SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
Copyright PMC
-
Sierra, Inc. 2003
FEATURES
Monolithic device integrating eight
T1/J1 or E1 short haul line interface
units.
Software switchable between T1/J1
and E1 operation on a per-device
basis.
Meets or exceeds T1/J1 and E1 short
haul network access specifications
including ANSI T1.102, T1.403,
T1.408, AT&T TR 62411, ITU-T G.703,
G.704 as well as ETSI 300-011, TBR
4, TBR 12, and TBR 13. In conjunction
with the TEMAP 84 (PM5366), allows
Add Drop Multiplexers and Terminal
Multiplexers to meet GR253, GR496,
and G.783.
Optional encoding/decoding of B8ZS,
HDB3, and AMI line codes.
Provides receive equalization, clock
recovery, and line performance
monitoring.
Provides transmit and receive jitter
attenuation.
Provides digitally programmable pulse
templates.
Provides a selectable, per channel
independent de-jittered T1 or E1
recovered clock for system timing and
redundancy.
Provides PRBS generators and
detectors on each tributary for error
testing at DS1 and E1 rates as
recommended in ITU-T O.151.
Uses line rate system clock.
SYSTEM INTERFACE
Supports transfer of transmitted single
rail PCM and signaling data from
1.544 Mbit/s and 2.048 Mbit/s
backplane buses or a SBI/SBI TR
interface for low pin count
interconnection of up to 11 OCTLIU
STs to the high-density PM5366
TEMAP 84 T1/E1 framer.
RECEIVE SECTION
Supports T1/E1 signal reception for
distances with up to 12dB of cable
attenuation at nominal conditions using
PIC 22 gauge cable emulation.
Supports G.772 compliant
non-intrusive protected monitoring
points.
Recovers clock and data using a digital
phase locked loop for high jitter
tolerance.
Tolerates more than 0.4 UI peak-to-
peak high frequency jitter as required
by AT&T TR 62411 and Bellcore
TR-TSY-000170.
Outputs dual rail recovered line pulses,
a single rail DS-1/E1 signal, or parallel
data in SBI/SBI TR bus format.
Performs B8ZS or AMI decoding when
processing a bipolar DS-1 signal and
HDB3 or AMI decoding when
processing a bipolar E1 signal.
Detects line code violations (LCVs),
B8ZS/HDB3 line code signatures, and
four (E1), eight (T1+B8ZS), or sixteen
(T1 AMI) successive zeros.
Provides a programmable depth FIFO
buffer for jitter attenuation, rate
conversion, and latency optimization in
the receive path.
TRANSMIT SECTION
Generates DSX-1 short haul pulses
with programmable pulse shape
compatible with AT&T, ANSI, and ITU
requirements.
REFCLK
AC1FP
DC1FP
XLPG
Transmit LIU
TXTIP1[8:1]
TXTIP2[8:1]
TXRING1[8:1]
TXRING2[8:1]
TJAT
Digital Jitter
Attenuator
LCODE
AMI / B8ZS /
HDB3 Line
Encoder
XPDE
Pulse Density
Enforcer
XIBC
Inband Loop-
back Code
Generator
PRBS
Pattern
Generator /
Detector
RLPS
Receive LIU
CDRC
Clk/Data
Recovery
PDVD
Pulse Density
Viol. Detector
IBCD
Inband Loop
back Code
Detector
RXTIP[8:1]
RXRING[8:1]
RJAT
Digital Jitter
Attenuator
LIU Octant x 8
PMON
Performance
Monitor
JTAG
uP Interface
H/W only
Auto-config
SBI
Insert
SBI
Extract
TDN[8:1]
TDP[8:1]
TCLK[8:1]
DDATA[7:0]
DDP
DPL
DV5
ADATA[7:0]
ADP
APL
AV5
AACTIVE
C1FPOUT
RDP[8:1]
RDN/RLCV[8:1]
RCLK[8:1]
(Line
Loopback)
(Diagnostic
Digital
Loopback)
LOS
Serial
Output
L
L
L
L
L
L
L
L
H
S
S
S
S
S
S
S
S
S
I
R
W
C
A
A
D
T
T
T
T
T
L
L
SBI TR
Extract
DSYNC
DDATA[7:0]
DPARITY
DALARM
DVALID
DFULL
DLINKRATE[5:0]
PISO
SIPO
SBI TR
Insert
AALARM
AVALID
ASYNC
APARITY
ALINKRATE[5:0]
RSTB
SBI_EN
TXHIZ/LineLB
CSD
Clock
Synthesis /
Distribution
TOPS
Timing
Options
XCLK
RSYNC
ADATA[7:0]
BLOCK DIAGRAM
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