Head Office:
PMC-Sierra, Inc.
8555 Baxter Place
Burnaby, B.C. V5A 4V7
Canada
Tel: +1.604.415.6000
Fax: +1.604.415.6200
Multi-rate Telecom Backplane SERDES for 2.5 Gbit/s Interconnect
To order documentation,
send email to:
document@pmc-sierra.com
or contact the head office,
Attn: Document Coordinator
info@pmc-sierra.com
PMC-2021208 (R4)
Copyright PMC-Sierra, Inc.
2005. All rights reserved.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USEReleased
PM5309 TBS 2488
All product documentation is available
on our web site at:
http://www.pmc-sierra.com
For corporate information,
send email to:
STS-1 BASED CROSS-CONNECTS AND MSPP’S
PM5309
TBS 2488
LIU
LIU
LIU
PM5385
ARROW
12xETEC
PM5309
TBS 2488
PM5316
SPECTRA 4x155
PM5309
TBS 2488
Optics
Optics
Optics
Optics
PM5332
SPECTRA 1x2488
PM5309
TBS 2488
Optics
Optics
Optics
Optics
MAG
MAG
MAG
PM4318
OCTLIU
PM4318
OCTLIU
PM5366
TEMAP 84
PM5366
TEMAP 84
PM5376
TSE Nx160
PM5377
TSE 240
PM5374
TSE 160
PM5372
TSE
PM5332
SPECTRA 1x2488
PM5309
TBS 2488
Optics
PM5332
SPECTRA 1x2488
PM5309
TBS 2488
Optics
OC-48 / STM-16
Ring
4x OC-12 / STM-4
4x OC-3 / STM-1
nxDS3/E3/EC-1
nxT1/E1
MSA-300
Optics
PM5327
ARROW-1x192
Optics
MSA-300
Optics
PM5327
ARROW-1x192
Optics
OC-192 / STM-64
Ring
Fabric Options
- Or -
- Or -
- Or -
TYPICAL APPLICATIONS
Provides Bit Error Rate (BER) monitoring
for all paths received on the TelecomBus
interface.
Detects signal degrade (SD-P) and signal
fail (SF-P) threshold crossing alarms
based on received B3 errors on the
TelecomBus interface.
ESSI FUNCTIONS
Automatically frames to the incoming
links based on standard A1/A2 framing.
Provides in-service link verification via bit
interleaved parity (BIP-8) of the B1 byte.
Optionally generates B1 byte on egress
flows.
Provides out of frame alignment status
information for each ingress port.
Provides per-link SONET-framed and
unframed PRBS-23 generation and
monitoring for off-line link verification.
Supports frame synchronization using
ESSI smart framing or a global frame
pulse input signal.
Compensates for in frame boundary
arrival times between serial interfaces
using FIFOs and device level software
configurable delay registers.
GENERAL
Low power 1.2 V CMOS core with 2.5 V or
3.3 V CMOS/TTL selectable digital I/O.
Generic 16-bit microprocessor bus
interface and full suite of interrupts for
configuration, control, and status
monitoring.
Standard 5-signal IEEE 1149.1 JTAG test
port for boundary scan board testing.
APPLICATIONS
Multi-service Provisioning Platforms.
SONET/SDH Digital Cross-connects.
SONET/SDH Add/Drop and Terminal
Multiplexers.