STANDARD PRODUCT
PMC-Sierra, Inc.
PM6344 EQUAD
PMC-951013
ISSUE 5
QUADRUPLE E1 FRAMER
168
10.2 Registers 049-04FH, 0C9H-0CFH, 149H-14FH, 1C9H-1CFH: Latching
Performance Data
All the Performance Data registers in one framer are updated as a group by
writing to any of the PMON block count registers (addresses 049H-04FH for
framer 1, 0C9H-0CFH for framer 2, 149H-14FH for framer 3, and 1C9H-1CFH for
framer 4). A write to any one of these locations loads performance data in the
associated PMON block into the internal holding registers (it is necessary to write
to one, and only one, count register address to latch all the count data register
values into the holding registers and to reset all the counters for each polling
cycle for the associated framer). Alternately, the Performance Data registers for
all four framers are updated by writing to the Revision/Chip ID/Global PMON
Update register (address 00CH). The data contained in the holding registers can
then be subsequently read by microprocessor accesses into the PMON block
count register address space. The latching of count data, and subsequent
resetting of the counters, is synchronized to the internal event timing so that no
events are missed.
The PMON is loaded with new performance data within 3.5 recovered clock
periods of the latch performance data register write. With nominal line rates, the
PMON registers should not be polled until 1.71μsec have elapsed from the "latch
performance data" register write.
When the EQUAD is reset, the contents of the PMON count registers are
unknown until the first latching of performance data is performed.