S/UNI-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
415
Figure 45 shows the S/UNI-ATLAS-3200 performing a back to back transfer. Two cells are
shown being transferred to the same PHY address (PHY 8) with a selection cycle in between.
S/UNI-ATLAS-3200 will always perform this selection between cells. In order for full
bandwidth support, TLU_CLAV must be asserted at least 5 clock cycles before the end of the
current transfer. See cycle 6. Note also that the ATM Layer device ignores TLU_CLAV
responses from the PHY up until cycle 14, for the purposes of deciding whether to transfer yet
another cell on the same PHY. The cycle after selection, cycle 12, is the first cycle it is valid for
the ATM Layer device to poll the selected PHY to determine if it has space for the next cell
transfer. This is to guarantee that the TLU_CLAV sent to the ATM Layer is not for the current
cell being serviced, but for the next cell transfer.
14.3
SRAM Interface
The S/UNI-ATLAS-3200 stores the search and linkage tables in up to 16M of external SRAM.
The SRAM may be in two 256Kx36 or one 256Kx72 units, and must be pipelined ZBT SRAM’s
rated for at least a 7ns cycle time. Only 8M of external SRAM (e.g. two 128Kx36) is required to
support 64K connections. However, up to 16M of RAM may be provisioned if the additional
search depth is desired. 18 address bits are provided, to support up to a 256Kx72 external SRAM.
If less SRAM is provisioned, the MSB of the RAM address should still be connected to
SADDR[17]; SADDR[16] may be left unconnected if only 8M of external SRAM is needed,
SADDR[16:15] if only 4M, and so on.
To facilitate timing from S/UNI-ATLAS-3200 to the SRAMs, the device drives the SRAM clock
(SRAMCLK_O) along with the address, data, and control signals. To facilitate timing from the
SRAM to the S/UNI-ATLAS-3200, a copy of SRAMCLK_O , called SYSCLK_O, must be fed
back into the device on the SYSCLK pin. This arrangement is illustrated in Figure 46.