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参数资料
| 型号： | PowerPC 440 |
| 厂商： | IBM Microeletronics |
| 英文描述： | 32-bit RISC PowerPC Embedded Processor Cores(32位 RISC PowerPC 嵌入式处理器) |
| 中文描述： | 32位RISC PowerPC嵌入式处理器内核（RISC的32位的PowerPC嵌入式处理器） |
| 文件页数： | 10/18页 |
| 文件大小： | 317K |
| 代理商： | POWERPC 440 |
PowerPC 440 Core
09/21/1999
Page 10 of 18
Memory Management Unit (MMU)
The MMU supports multiple page sizes as well as a variety of storage protection attributes and access
control options. Multiple page sizes improve TLB efficiency and minimize the number of TLB misses.
The PPC440 gives programmers the flexibility to have any combination of the following eight possible
page sizes in the translation look-aside buffer (TLB) simultaneously: 1KB, 4KB, 16KB, 64KB, 256KB,
1MB, 16MB and 256MB. Having an extremely large page size allows users to define system memory
with a minimal number of TLB entries, thereby simplifying TLB allocation and replacement. Small page
sizes prevent the wasting of memory when allocating small areas of data.
Each page of memory is accompanied by a set of storage attributes. These attributes include cacheability,
write through/write back mode, big/little endian, guarded and four user-defined attributes. The user-
defined attributes can be used to mark a memory page with an application-specific meaning. The guarded
attribute controls speculative accesses. The big/little endian attribute marks a memory page as having big
or little endian byte ordering. Write through/write back specifies whether memory is updated in addition
to the cache during store operations.
Two of the user-defined storage attributes can be programmed for special functions inside the core. One
can be enabled to designate normal or transient cache regions. Another can be enabled to control whether
or not store misses allocate a line in the D-Cache.
Access control bits in the TLB entries enable system software to control read, write, and execute access for
programs in both user and supervisor states.
The MMU includes a 64-entry fully-associative unified TLB to reduce the overhead of address translation.
Contention for the main TLB between data address and instruction address translation is minimized
through the use of a four-entry instruction shadow TLB (ITLB) and an eight-entry data shadow TLB
(DTLB). The ITLB and DTLB shadow the most recently used entries in the unified TLB. The MMU
manages the replacement strategy of the ITLB and DTLB leaving the unified TLB to software control.
Real-time operating systems are free to implement their own replacement algorithm for the unified TLB.
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