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参数资料
| 型号： | PPC5567MVR132 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 5/68页 |
| 文件大小： | 0K |
| 描述： | MCU 32BIT POWERPC 416-PBGA |
| 标准包装： | 200 |
| 系列： | MPC55xx Qorivva |
| 核心处理器： | e200z6 |
| 芯体尺寸： | 32-位 |
| 速度： | 132MHz |
| 连通性： | CAN，EBI/EMI，以太网，SCI，SPI |
| 外围设备： | DMA，POR，PWM，WDT |
| 输入/输出数： | 238 |
| 程序存储器容量： | 2MB（2M x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 80K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 1.35 V ~ 1.65 V |
| 数据转换器： | A/D 40x12b |
| 振荡器型： | 外部 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 416-BBGA |
| 包装： | 托盘 |
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Electrical Characteristics
MPC5567 Microcontroller Data Sheet, Rev. 2
Freescale
13
3.7.1
Input Value of Pins During POR Dependent on VDD33
When powering up the device, VDD33 must not lag the latest VDDSYN or RESET power pin (VDDEH6) by
more than the VDD33 lag specification listed in Table 6, spec 8. This avoids accidentally selecting the
bypass clock mode because the internal versions of PLLCFG[0:1] and RSTCFG are not powered and
therefore cannot read the default state when POR negates. VDD33 can lag VDDSYN or the RESET power
pin (VDDEH6), but cannot lag both by more than the VDD33 lag specification. This VDD33 lag specification
applies during power up only. VDD33 has no lead or lag requirements when powering down.
3.7.2
Power-Up Sequence (VRC33 Grounded)
The 1.5 V VDD power supply must rise to 1.35 V before the 3.3 V VDDSYN power supply and the RESET
power supply rises above 2.0 V. This ensures that digital logic in the PLL for the 1.5 V power supply does
not begin to operate below the specified operation range lower limit of 1.35 V. Because the internal 1.5 V
POR is disabled, the internal 3.3 V POR or the RESET power POR must hold the device in reset. Since
they can negate as low as 2.0 V, VDD must be within specification before the 3.3 V POR and the RESET
POR negate.
Figure 3. Power-Up Sequence (VRC33 Grounded)
3.7.3
Power-Down Sequence (VRC33 Grounded)
The only requirement for the power-down sequence with VRC33 grounded is if VDD decreases to less than
its operating range, VDDSYN or the RESET power must decrease to less than 2.0 V before the VDD power
increases to its operating range. This ensures that the digital 1.5 V logic, which is reset only by an ORed
POR and can cause the 1.5 V supply to decrease less than its specification value, resets correctly. See
Table 6, footnote 1.
VDDSYN and RESET Power
VDD
2.0 V
1.35 V
VDD must reach 1.35 V before VDDSYN and the RESET power reach 2.0 V
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