参数资料
型号: PRM48BF480T400A00
元件分类: 稳压器
英文描述: 8.33 A SWITCHING REGULATOR, 1000 kHz SWITCHING FREQ-MAX, DMA24
封装: ROHS COMPLIANT PACKAGE-24
文件页数: 14/22页
文件大小: 1097K
代理商: PRM48BF480T400A00
Rev. 1.1
12 / 2010
Page 21 of 22
PRM48BF480T400A00
(Formerly VIP0001TFJ)
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
10.5.2 Inductive
source
and
local,
external
input
decoupling capacitance with significant RCIN_EXT ESR (i.e.:
electrolytic type)
In order to simplify the analysis in this case, the voltage
source impedance can be modeled as a simple inductor
Lline. Notice that, the high performance ceramic capacitors
CIN_INT within the PRM should be included in the external
electrolytic capacitance value for this purpose. The
stability criteria will be
EXT
IN
C
IN
EQ
R
r
_
[8]
IN
EQ
C
EXT
IN
line
r
R
C
L
EXT
IN
_
[9]
Equation [9] shows that if the aggregate ESR is too small
– for example by using very high quality input capacitors
(CIN_EXT) – the system will be under-damped and may even
become destabilized. Again, an octave of design margin in
satisfying [8] should be considered the minimum.
10.6
Arrays
Up to ten PRMs of the same type may be placed in
parallel to expand the power capacity of the system. The
following high-level guidelines must be followed in order
for the resultant system to start up and operate properly,
and to avoid overstress or exceeding any absolute
maximum ratings.
–IN pins of all PRMs must be connected together.
Both inductance and resistance from the common
power source to each PRM should be minimized,
and matched.
Input voltage to all PRMs must be the same.
Independent
fuses
for
each
PRM
are
recommended.
PC pins must be connected together for
synchronization and proper fault response.
Reference supply to the control loop voltage
reference and current sense circuitry must be
enabled when all modules’ RE pins have reached
their operational voltage levels.
There must be one single external voltage control
loop. The control loop must drive each PR pin
relative to each modules’ SG pin, and the local PR
voltage must be the same across all modules.
Each PRM must have its own local current shunt
and current sense circuitry to drive it’s IF pin.
The number of PRMs required to achieve a given
array capacity must consider all sources of
mismatch to avoid overstress of any PRM in the
array. Imbalances in sharing are not only due to
current sharing accuracy specifications, but also
temperature
differences
among
PRMs,
Vin
variations, and error terms in the buffering of the
error amplifier output to the PR pins.
Control loop compensation procedures above will
hold for an array, in general, although many
parameters must be scaled against the number of
PRMs in the system.
Please contact Vicor Applications for assistance.
10.7
Input Fuse Recommendations
A fuse should be incorporated at the input to each PRM, in
series with the +IN pin. A 15A or smaller input fuse
(Littelfuse
NANO2 451/453 Series, or equivalent) is
required to safety agency conditions of acceptability.
Always ascertain and observe the safety, regulatory, or
other agency specifications that apply to your specific
application.
10.8
Layout considerations
Application Note AN:005 details board layout using VI
Chip components. Additional consideration must be given
to the external control circuit components.
The current sense shunt signal voltage is highly sensitive
to noise. As such, current sensing circuitry should be
located close to the shunt to minimize the length of the
sense signals. A Kelvined connection at the shunt is
recommended for best results.
The control signal from a remote voltage sense circuit to
the PRM should be shielded. Avoid routing this, or other
control signals directly underneath the PRM, if possible.
Components that tie directly to the PRM should be located
close to their respective pins. It is also critical that all
control components be referenced to SG, and that SG not
be tied to any other ground in the system, including –IN or
–OUT of the PRM.
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