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参数资料
| 型号： | PSD413A2F |
| 英文描述： | Field Programmable Microcontroller Peripherals with Flash Memory(可编程逻辑，16K位SRAM,35个可编程I/O,通用PLD有59个输入) |
| 中文描述： | 现场可编程微控制器外围设备与快闪记忆体（可编程逻辑，16K的位的SRAM，35余个可编程输入/输出，通用PLD的有59个输入） |
| 文件页数： | 4/98页 |
| 文件大小： | 365K |
| 代理商： | PSD413A2F |
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PSD413F Family
6-4
ADVANCE INFORMATION
The PSD4XX series of Field Programmable Microcontroller Peripherals represent a major
advance in the evolution of Programmable Peripherals. They combine an innovative
architecture with state of the art technology to provide user
PROGRAMMABILITY
(logic, functions, memory), flexibility, high integration, optimum performance, and low power.
The PSD413F is the first PSD product that provides In-System Programming of the
non-volatile program memory. The Flash memory is a 1 Mbit 5 volt-only read/write/erase
memory that includes the embedded algorithms for performing those functions on-chip.
Figure 1 is a top level block diagram of the PSD413A2F.
At the core of the PSD413F are two dedicated ZPLDs that are based on the functions they
perform:
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Decoding ZPLD (DPLD)
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General Purpose ZPLD (GPLD)
Both ZPLDs receive the same inputs through the ZPLD bus and are differentiated by their
output destinations. The DPLD’s main function is to perform address space decoding for the
internal I/O Ports, Peripherals, Boot EPROM, and standby SRAM. The address decoding
can be based on any address input, control signal (RD, PSEN) and page logic. Address
inputs originate from either the microcontroller interface (ADIO Port) or other I/O Ports for
additional decoding. The DPLD allows for efficient mapping of the boot memory and SRAM
for general and Flash read/write operations. The DPLD also supports special requirements
of 8031 architecture based designs that need to store data in the EPROM or execute
programs from the SRAM.
The GPLD is a general purpose ZPLD that can perform many functions:
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Extend the address decoding of the MCU to the 1 Mbit Flash memory.
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Extend the address decoding of the MCU to external peripherals.
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Implement general purpose state machines and logic functions.
The GPLD has up to 59 inputs, 118 product terms, 24 flexible macrocells and 24 I/O pins
that are connected to Port A, B and E macrocells. Five macrocells are dedicated to control
the Flash memory (CSF, RDF, WRF, A15F, A16F). These macrocells enable implementation
of very efficient MCU address decoding schemes of the Flash memory in both program and
data address space. In addition, the GPLD can implement other logic functions such as
state machines and random logic.
The ZPLDs are designed to consume minimum power by using Zero Power design
techniques. A configuration bit (Turbo bit) that can be set by the MCU will turn the ZPLDs
off (into standby) automatically if no inputs are changing. Any unused product term will be
turned off during programming and will not consume any power in the system.
The PSD413F has 35 I/O pins that are divided into 5 ports. Each I/O pin can be individually
configured to provide many functions. Ports A, B and E have the capability to be configured
as standard MCU I/O ports, GPLD I/O, and latched address outputs for multiplexed
address/data controllers. Ports C and D can be used as general purpose I/O ports and
PLD inputs. In the PSD413FN, Port C is a dedicated data bus for microcontrollers with a
non-multiplexed bus.
The PSD413F can easily interface with no “glue logic” to a variety of 8- and 16-bit
microcontrollers with a multiplexed or non-multiplexed bus. All the control signals are
connected to the two ZPLDs enabling the user to generate timing and decoding signals for
external peripherals. For controllers that do not have a Reset output, the PSD413F can
generate a RESET output based on its RESET input that includes hysteresis.
General
Description
相关PDF资料 |
PDF描述 |
|---|---|
| PSD4235G2(中文) | Flash In-System-Programmable Peripherals for 16-Bit MCUs(用于16位MCU的闪速在系统可编程外围芯片) |
| PSD4235G2 | Flash In-System-Programmable Peripherals for 16-Bit MCUs(用于16位MCU的闪速在系统可编程外围芯片) |
| PSD4235G2 | FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERALS FOR 16-BIT MCUS (5V SUPPLY) |
| PSD4235G2V | -200V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a TO-254AA package; A JANSR2N7426 with Standard Packaging |
| PSD4235G1-B-12J | Flash In-System Programmable ISP Peripherals For 16-bit MCUs 5V Supply |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PSD4-16 | 制造商:Tamura Corporation of America 功能描述: |
| PSD4-20 | 制造商:MICROTRAN 功能描述:POWER TRANSFORMER, 6 VA |
| PSD4235G2-70U | 功能描述:SPLD - 简单可编程逻辑器件 5.0V 4M 70ns RoHS:否 制造商:Texas Instruments 逻辑系列:TICPAL22V10Z 大电池数量:10 最大工作频率:66 MHz 延迟时间:25 ns 工作电源电压:4.75 V to 5.25 V 电源电流:100 uA 最大工作温度:+ 75 C 最小工作温度:0 C 安装风格:Through Hole 封装 / 箱体:DIP-24 |
| PSD4235G2-90U | 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| PSD4235G2-90UI | 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
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