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参数资料
| 型号： | PSD4235F1-C-90UI |
| 厂商： | 意法半导体 |
| 英文描述： | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| 中文描述： | Flash在系统可编程外设的16位微控制器 |
| 文件页数： | 22/93页 |
| 文件大小： | 503K |
| 代理商： | PSD4235F1-C-90UI |
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Preliminary Information
PSD4000 Series
19
The
PSD4000
Functional
Blocks
(cont.)
9.1.1.5.5 Data Polling Flag DQ7 (DQ15 for Motorola)
When Erasing or Programming the Flash memory bit DQ7 (DQ15) outputs the complement
of the bit being entered for Programming/Writing on DQ7 (DQ15). Once the Program
instruction or the Write operation is completed, the true logic value is read on DQ7 (DQ15)
(in a Read operation). Flash memory specific features:
J
Data Polling is effective after the fourth Write pulse (for programming) or after the
sixth Write pulse (for Erase). It must be performed at the address being programmed
or at an address within the Flash sector being erased.
J
During an Erase instruction, DQ7 (DQ15) outputs a ‘0’. After completion of the
instruction, DQ7 (DQ15) will output the last bit programmed (it is a ‘1’ after erasing).
J
If the location to be programmed is in a protected Flash sector, the instruction is
ignored.
J
If all the Flash sectors to be erased are protected, DQ7 (DQ15) will be set to ‘0’ for
about 100 μs, and then return to the previous addressed location. No erasure will be
performed.
9.1.1.5.6 Toggle Flag DQ6 (DQ14 for Motorola)
The PSD4000 offers another way for determining when the Flash memory Program
instruction is completed. During the internal Write operation and when either the FSi or
CSBOOTi is true, the DQ6 (DQ14) will toggle from ‘0’ to ‘1’ and ‘1’ to ‘0’ on subsequent
attempts to read any word of the memory.
When the internal cycle is complete, the toggling will stop and the data read on the
Data Bus is the addressed memory location. The device is now accessible for a new
Read or Write operation. The operation is finished when two successive reads yield the
same output data. Flash memory specific features:
J
The Toggle bit is effective after the fourth Write pulse (for programming) or after the
sixth Write pulse (for Erase).
J
If the location to be programmed belongs to a protected Flash sector, the instruction
is ignored.
J
If all the Flash sectors selected for erasure are protected, DQ6 (DQ14) will toggle to
‘0’ for about 100 μs and then return to the previous addressed location.
9.1.1.5.7 Error Flag DQ5 (DQ14 for Motorola)
During a correct Program or Erase, the Error bit will set to ‘0’. This bit is set to ‘1’ when
there is a failure during Flash programming, Sector erase, or Bulk Erase.
In the case of Flash programming, the Error Bit indicates the attempt to program a Flash
bit(s) from the programmed state (0) to the erased state (1), which is not a valid operation.
The Error bit may also indicate a timeout condition while attempting to program a word.
In case of an error in Flash sector erase or word program, the Flash sector in which the
error occurred or to which the programmed location belongs must no longer be used.
Other Flash sectors may still be used. The Error bit resets after the Reset instruction. A
reset instruction is required after detecting the error bit.
9.1.1.5.8 Erase Time-out Flag DQ3 (DQ11 for Motorola)
The Erase Timer bit reflects the time-out period allowed between two consecutive Sector
Erase instructions. The Erase timer bit is set to ‘0’ after a Sector Erase instruction for a
time period of 100 μs + 20% unless an additional Sector Erase instruction is decoded.
After this time period or when the additional Sector Erase instruction is decoded, DQ3
(DQ11) is set to ‘1’. A reset instruction is required after detecting the erase timer bit.
相关PDF资料 |
PDF描述 |
|---|---|
| PSD4235F2-15UI | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4235F2-70UI | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4235F2-90B81 | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4235F2-90B81I | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4235F2-90J | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PSD4235G2-70U | 功能描述:SPLD - 简单可编程逻辑器件 5.0V 4M 70ns RoHS:否 制造商:Texas Instruments 逻辑系列:TICPAL22V10Z 大电池数量:10 最大工作频率:66 MHz 延迟时间:25 ns 工作电源电压:4.75 V to 5.25 V 电源电流:100 uA 最大工作温度:+ 75 C 最小工作温度:0 C 安装风格:Through Hole 封装 / 箱体:DIP-24 |
| PSD4235G2-90U | 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| PSD4235G2-90UI | 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| PSD4235G2V-12UI | 功能描述:CPLD - 复杂可编程逻辑器件 3.3V 4M 120ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| PSD4235G2V-90U | 功能描述:CPLD - 复杂可编程逻辑器件 3.3V 4M 90ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
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