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| 型号： | PSD4235G2V-A-20B81 |
| 厂商： | 意法半导体 |
| 英文描述： | Tantalum Electrolytic Capacitor; Capacitance:100uF; Capacitance Tolerance:+/- 20 %; Working Voltage, DC:10V; Package/Case:7343-31; Terminal Type:PCB SMT; ESR:0.0055ohm; Dielectric Material:Tantalum; Operating Temp. Max:105 C |
| 中文描述： | Flash在系统可编程外设的16位微控制器 |
| 文件页数： | 4/93页 |
| 文件大小： | 503K |
| 代理商： | PSD4235G2V-A-20B81 |
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Preliminary Information
PSD4000 Series
Pin*
(TQFP
Pin Name Pkg.)
Type
Description
Reset
39
I
Active low input. Resets I/O Ports, PLD Micro
Cells, some of
the configuration registers and JTAG registers. Must be active
at power up. Reset also aborts the Flash programming/erase
cycle that is in progress.
PA0-PA7
51-58
I/O
Port A, PA0-7. This port is pin configurable and has multiple
CMOS
functions:
or Open
1. MCU I/O — standard output or input port
Drain
2. GPLD output.
3. Input to the PLD (can also be PLD input for address A16
and above).
PB0-PB7
61-68
I/O
Port B, PB0-7. This port is pin configurable and has multiple
CMOS
functions:
or Open
1. MCU I/O — standard output or input port.
Drain
2. GPLD output.
3. Input to the PLD (can also be PLD input for address A16
and above).
PC0-PC7 41-48
I/O
Port C, PC0-7. This port is pin configurable and has multiple
CMOS
functions:
or Slew
1. MCU I/O — standard output or input port.
Rate
2. External chip select (ECS0-7) output.
3. Input to the PLD (can also be PLD input for address A16
and above).
PD0
79
I/O
Port D pin PD0 can be configured as:
CMOS
1. ALE or AS input — latches addresses on ADIO0-15 pins
or Open
2. AS input — latches addresses on ADIO0-15 pins on the
Drain
rising edge.
3. Input to the PLD (can also be PLD input for address A16
and above).
PD1
80
I/O
Port D pin PD1 can be configured as:
CMOS
1. MCU I/O
or Open
2. Input to the PLD (can also be PLD input for address A16
Drain
and above).
3. CLKIN clock input — clock input to the GPLD
Micro
Cells, the APD power down counter and GPLD
AND Array.
PD2
1
I/O
Port D pin PD2 can be configured as:
CMOS
1. MCU I/O
or Open
2. Input to the PLD (can also be PLD input for address A16
Drain
and above).
3. CSI input — chip select input. When low, the CSI enables
the internal PSD memories and I/O. When high, the
internal memories are disabled to conserve power. CSI
trailing edge can get the part out of power-down mode.
PD3
2
I/O
Port D pin PD3 can be configured as:
CMOS
1. MCU I/O
or Open
2. Input to the PLD (can also be PLD input for address A16
Drain
and above).
3. WRH — for 16-bit data bus, write to high byte, active low.
PE0
71
I/O
Port E, PE0. This port is pin configurable and has multiple
CMOS
functions:
or Open
1. MCU I/O — standard output or input port.
Drain
2. Latched address output.
3. TMS input for JTAG/ISP interface.
Table 5.
PSD4000
Pin
Descriptions
(cont.)
9
相关PDF资料 |
PDF描述 |
|---|---|
| PSD4235G2V-A-20B81I | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4235G2V-A-70M | Conductive Polymer Chip Capacitors / T520 Series - KO Cap; Capacitance [nom]: 150uF; Working Voltage (Vdc)[max]: 6.3V; Capacitance Tolerance: +/-20%; Dielectric: Conductive Polymer; ESR: 15mΩ; Lead Style: Surface-Mount Chip; Lead Dimensions: 7343-31; Termination: 100% Tin (Sn); Body Dimensions: 7.3mm x 4.3mm x 2.8mm; Temperature Range: -55C to +105C; Container: Tape & Reel; Qty per Container: 500; Features: Low ESR |
| PSD4235G2V-A-70MI | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
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