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| 型号： | PSD4235G2V-A-20B81 |
| 厂商： | 意法半导体 |
| 英文描述： | Tantalum Electrolytic Capacitor; Capacitance:100uF; Capacitance Tolerance:+/- 20 %; Working Voltage, DC:10V; Package/Case:7343-31; Terminal Type:PCB SMT; ESR:0.0055ohm; Dielectric Material:Tantalum; Operating Temp. Max:105 C |
| 中文描述： | Flash在系统可编程外设的16位微控制器 |
| 文件页数： | 61/93页 |
| 文件大小： | 503K |
| 代理商： | PSD4235G2V-A-20B81 |
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9.5.3.4 Reset of Flash Erase and Programming Cycles
An external reset on the RESET pin will also reset the internal Flash memory state
machine. When the Flash is in programming or erase mode, the RESET pin will terminate
the programming or erase operation and return the Flash back to read mode in tNLNH-A
(minimum 25 s) time.
9.6 Programming In-Circuit using the JTAG-ISP Interface
The JTAG-ISP interface on the PSD4000 can be enabled on Port E (see Table 29). All
memory (Flash and Flash Boot Block), PLD logic, and PSD configuration bits may be
programmed through the JTAG-ISC interface. A blank part can be mounted on a printed
circuit board and programmed using JTAG-ISP.
The standard JTAG signals (IEEE 1149.1) are TMS, TCK, TDI, and TDO. Two additional
signals, TSTAT and TERR, are optional JTAG extensions used to speed up program and
erase operations.
Preliminary Information
PSD4000 Series
61
Port E Pin
JTAG Signals
Description
PE0
TMS
Mode Select
PE1
TCK
Clock
PE2
TDI
Serial Data In
PE3
TDO
Serial Data Out
PE4
TSTAT
Status
PE5
TERR
Error Flag
Table 29. JTAG Port Signals
The
PSD4000
Functional
Blocks
(cont.)
*SR_cod bit in the VM Register are always cleared to zero on power on or warm reset.
Port Configuration
Power On Reset
Warm Reset
Power Down Mode
MCU I/O
Input Mode
Unchanged
PLD Output
Valid after internal
Valid
Depend on inputs to
PSD configuration
PLD (address are
bits are loaded
blocked in PD mode)
Address Out
Tri-stated
Not defined
Data Port
Tri-stated
Table 28. Status During Power On Reset, Warm Reset and Power Down Mode
Register
Power On Reset
Warm Reset
Power Down Mode
PMMR0, 2
Cleared to “0”
Unchanged
VM Register*
Initialized based on
Unchanged
the selection in
PSDsoft
Configuration Menu.
All other registers
Cleared to “0”
Unchanged
By default, on a blank PSD (as shipped from factory or after erasure), four pins on Port E
are enabled for the basic JTAG signals TMS, TCK, TDI, and TDO.
See Application Note 54 for more details on JTAG In-System-Programming.
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| PSD4235G2V-A-20B81I | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4235G2V-A-70M | Conductive Polymer Chip Capacitors / T520 Series - KO Cap; Capacitance [nom]: 150uF; Working Voltage (Vdc)[max]: 6.3V; Capacitance Tolerance: +/-20%; Dielectric: Conductive Polymer; ESR: 15mΩ; Lead Style: Surface-Mount Chip; Lead Dimensions: 7343-31; Termination: 100% Tin (Sn); Body Dimensions: 7.3mm x 4.3mm x 2.8mm; Temperature Range: -55C to +105C; Container: Tape & Reel; Qty per Container: 500; Features: Low ESR |
| PSD4235G2V-A-70MI | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
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