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参数资料
| 型号： | PSD511B1 |
| 英文描述： | Field Programmable Microcontroller Peripherals(可编程逻辑，16K位SRAM,40个可编程I/O,通用PLD有61个输入) |
| 中文描述： | 现场可编程微控制器外围设备（可编程逻辑，16K的位的SRAM，40余个可编程输入/输出，通用PLD的有61个输入） |
| 文件页数： | 12/130页 |
| 文件大小： | 704K |
| 代理商： | PSD511B1 |
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PSD5XX Famly
6-12
The DPLD
The DPLD is used for internal address decoding generating the following eight
chip select signals:
J
ES0 – ES3
EPROM selects, block 0 to block 3
J
RS0
SRAM block select
J
CSIOP
I/O Decoder chip select
J
PSEL0 – PSEL1
Peripheral I/O mode select signals
The I/O Decoder enabled by the CSIOP generates chip selects for on-chip registers or I/O
ports based on address inputs A[7:0].
As shown in Figure 4, the DPLD consists of a large programmable AND ARRAY. There are
a total of 61 inputs and 8 outputs. Each output consists of a single product term. Although
the user can generate select signals from any of the inputs, the select signals are typically a
function of the address and Page Register inputs. The select signals, which are active High,
are defined by the user in the ABEL file (PSDabel).
The address line inputs to the DPLD include A0, A1 and A8 – A15. If more address lines
are needed, the user can bring in the lines through Port A to the DPLD.
The GPLD
The structure of the General Purpose PLD consists of a programmable AND ARRAY and
3 sets of I/O Macrocells. The ARRAY has 61 input signals, same as the DPLD. From these
inputs, “ANDed” functions are generated as product term inputs to the macrocells. The I/O
Macrocell sets are named after the I/O Ports they are linked to, e.g., the macrocells
connected to Port A are named PA Macrocells. The 3 sets of macrocells, PA, PB and PE,
are similar in structure and function.
Figure 5 shows the output/input path of a GPLD macrocell to the Port pin with which it is
associated. If the Port pin is specified as a GPLD output pin in PSDsoft, the MUX in the I/O
Port Cell selects the GPLD macrocell as an output of the Port pin. The output enable signal
to the buffer in the I/O cell can be controlled by a product term from the AND ARRAY.
If the Port pin is specified as a ZPLD input pin, the MUX in the GPLD macrocell selects the
Port input signal to be one of the 61 signals in the ZPLD Input Bus.
ZPLDBlock
(Cont.)
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PDF描述 |
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| PSD502B1 | Field Programmable Microcontroller Peripherals(可编程逻辑，16K位SRAM,40个可编程I/O,通用PLD有61个输入) |
| PSD503B1 | Field Programmable Microcontroller Peripherals(可编程逻辑，16K位SRAM,40个可编程I/O,通用PLD有61个输入) |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PSD511B1-12J | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field-Programmable Peripheral |
| PSD511B1-12JI | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field-Programmable Peripheral |
| PSD511B1-12LI | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field-Programmable Peripheral |
| PSD511B1-12U | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field-Programmable Peripheral |
| PSD511B1-12UI | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field-Programmable Peripheral |
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