参数资料
型号: PSD603E1
英文描述: Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可编程逻辑,4K位SRAM,26个可编程I/O,通用PLD有63个输入)
中文描述: 现场可编程微控制器外围设备和嵌入式微-细胞(可编程逻辑,4K的位的SRAM,26我个可编程输入/输出,通用PLD的有63个输入)
文件页数: 14/84页
文件大小: 426K
代理商: PSD603E1
PSD6XX Family
11-14
Each of the three PLDs has unique characteristics suited for its applications. They are
described in the following sections.
Decode PLD
The Decode PLD (DPLD), shown in Figure 4, is used to select the internal PSD6XXE1
functions: EPROM blocks, SRAM, Registers (CSIOP) and the Port A Peripheral Mode.
All the select signals are active high and have one product term, except ES7 which has two.
The CSIOP is the select line for the PSD6XXE1 internal registers that occupies 256 bytes
of memory space. A second level decoder selects a register based on the address
inputs A[7-0].
Each EPROM block has its own chip select. The chip select of the eighth EPROM
block has two product terms, ES7A and ES7B. This allows the eighth block to reside
in two memory spaces, where ES7B can typically select reset vectors or configuration
bytes that are stored in the MCU address space.
PSEL 0 & 1 are used as inputs to Port A to control the port’s Peripheral I/O mode
operation. Usually PSEL 0&1 are defined in term of the MCU address inputs. This mode is
explained in the I/O Port section.
PLDs
(cont.)
Input Source
Input Name
Number of Bits
MCU Address Bus
A[15:0]
*
16
I/O Ports
Port A, B, C
PA[7:0], PB[7:0]
PC[7:3], PC[1:0]
23
Page Register
PGR[3:0]
4
Control Signal
CNTL1 (Read)
1
Reset Pin
RST
1
Table 7. DPLD Inputs
*
NOTE:
The address inputs are A[19:4] in 80C51XA mode, A[3:0] are assigned to Port A.
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相关代理商/技术参数
参数描述
PSD603E1-70L 制造商:WSI 功能描述:
PSD60-A 制造商:WALL 制造商全称:Wall Industries,Inc. 功能描述:60 Watt Dual Output AC/DC Power Supply
PSD60-B 制造商:WALL 制造商全称:Wall Industries,Inc. 功能描述:60 Watt Dual Output AC/DC Power Supply
PSD61 制造商:POWERSEM 制造商全称:POWERSEM 功能描述:Three Phase Rectifier Bridges
PSD611E1-15J 制造商:WSI 功能描述: 制造商:WSI 功能描述:32K X 8 OTPROM, 26 I/O, PIA-GENERAL PURPOSE, PQCC52