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参数资料
| 型号： | PSD612E1 |
| 英文描述： | Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可编程逻辑，4K位SRAM,26个可编程I/O,通用PLD有63个输入) |
| 中文描述： | 现场可编程微控制器外围设备和嵌入式微-细胞（可编程逻辑，4K的位的SRAM，26我个可编程输入/输出，通用PLD的有63个输入） |
| 文件页数： | 12/84页 |
| 文件大小： | 426K |
| 代理商： | PSD612E1 |
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PSD6XX Family
11-12
The PSD6XXE1
Functional
Blocks
The PSD6XXE1 consists of five major functional blocks:
J
PLD Block
J
Bus Interface
J
I/O Ports
J
Memory Block
J
Power Management Unit
The functions of each block are described in the following sections. Many of the blocks
perform multiple functions, and are user configurable.
PLDs
The PLDs bring programmable logic functionality to the PSD6XXE1. After
specifying the logic for the PLDs by using the PSDabel tool in the PSDsoft suite, the logic
configuration is programmed into the device and available when power is applied.
The PLDs (DPLD, ECSPLD and GPLD) consist of an AND array. The GPLD architecture
includes 12 Output Micro
Cells in addition to the AND array. There are 23 Input
Micro
Cells that can be configured as inputs to the PLD. Figure 3 shows the organization
of the PLD.
The AND array is used to form product terms specified using the PSDabel tool in the
PSDsoft development system. When the inputs used in a term are true, the output is active.
The GPLD Input Bus consists of 63 signals as shown in Table 6. Both the true and
complement value of inputs are available to the AND array. The DPLD and ECSPLD Input
Busses consists of fewer inputs and is a subset of the 63 inputs.
Input Source
Input Name
Number of Signals
MCU Address Bus
A[15:0]*
16
MCU Control Signals
CNTL[2:0]
3
Reset
RST
1
Power Down
PDN
1
I/O Ports Inputs (Input Micro
Cells)
PA[7:0], PB[7:0]
PC[7:3], PC[1:0]
23
Port D Inputs
PD[2:0]
3
Page Register
PGR[3:0]
4
Port A or B Micro
Cell Feedback
Port C Micro
Cell Feedback
MCELLAB.FB[7:4]
4
MCELLC.FB[7:0]
8
Table 6. GPLD Inputs
*
NOTE:
The address inputs are A[19:4] in 80C51XA mode.
相关PDF资料 |
PDF描述 |
|---|---|
| PSD613E1 | Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可编程逻辑，4K位SRAM,26个可编程I/O,通用PLD有63个输入) |
| PSD703S5 | Field Programmable Microcontroller Peripherals with Supervisory Functions(可编程逻辑，4K位SRAM,27个可编程I/O,通用PLD有66个输入) |
| PSD701S5 | Field Programmable Microcontroller Peripherals with Supervisory Functions(可编程逻辑，4K位SRAM,27个可编程I/O,通用PLD有66个输入) |
| PSD702S5 | Field Programmable Microcontroller Peripherals with Supervisory Functions(可编程逻辑，4K位SRAM,27个可编程I/O,通用PLD有66个输入) |
| PSD711S5 | Field Programmable Microcontroller Peripherals with Supervisory Functions(可编程逻辑，4K位SRAM,27个可编程I/O,通用PLD有66个输入) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PSD612E1-15J | 制造商:WSI 功能描述: |
| PSD612E1-15JI | 制造商:WSI 功能描述: 制造商:WSI 功能描述:64K X 8 OTPROM, 26 I/O, PIA-GENERAL PURPOSE, PQCC52 |
| PSD612E1-70J | 制造商:WSI 功能描述: |
| PSD612E1-70L | 制造商:WSI 功能描述: |
| PSD612E1-90JI | 制造商:WSI 功能描述: |
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