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| 型号： | PSD8134V90JT |
| 厂商： | 意法半导体 |
| 英文描述： | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| 中文描述： | Flash在系统可编程ISP的外设的8位微控制器 |
| 文件页数： | 69/110页 |
| 文件大小： | 1685K |
| 代理商： | PSD8134V90JT |
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PSD813F1
RESET TIMING AND DEVICE STATUS AT RESET
Power-On Reset
Upon Power-up, the PSD requires a Reset (RE-
SET) pulse of duration t
NLNH-PO
(See Tables
67
and
68
for values) after V
CC
is steady. During this
period, the device loads internal configurations,
clears some of the registers and sets the Flash
memory or EEPROM into Operating mode. After
the rising edge of Reset (RESET), the PSD re-
mains in the Reset mode for an additional period,
t
OPR
(See Tables
67
and
68
for values), before the
first memory access is allowed.
The PSD Flash or EEPROM memory is reset to
the READ mode upon power up. The FSi and
EESi select signals along with the write strobe sig-
nal must be in the false state during power-up re-
set for maximum security of the data contents and
to remove the possibility of a byte being written on
the first edge of a write strobe signal. The PSD au-
tomatically prevents write strobes from reaching
the EEPROM memory array for about 5ms (t
EEH-
WL
). Any Flash memory WRITE cycle initiation is
prevented automatically when V
CC
is below V
LKO
.
Warm Reset
Once the device is up and running, the device can
be reset with a much shorter pulse of t
NLNH
(See
Tables
67
and
68
for values). The same t
OPR
time
is needed before the device is operational after
warm reset. Figure
35
shows the timing of the
power on and warm reset.
I/O Pin, Register and PLD Status at Reset
Table 33., page 70
shows the I/O pin, register and
PLD status during Power On Reset, Warm reset
and Power-down mode. PLD outputs are always
valid during warm reset, and they are valid in Pow-
er On Reset once the internal PSD Configuration
bits are loaded. This loading of PSD is completed
typically long before the V
CC
ramps up to operat-
ing level. Once the PLD is active, the state of the
outputs are determined by the PSDabel equa-
tions.
Figure 35. Reset (RESET) Timing
tNLNH-PO
Power-On Reset
tOPR
AI02866b
RESET
tNLNH
tNLNH-A
Warm Reset
tOPR
V
CC
V
CC
(min)
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