参数资料
型号: PSD8134V90JT
厂商: 意法半导体
英文描述: Flash In-System Programmable ISP Peripherals For 8-bit MCUs
中文描述: Flash在系统可编程ISP的外设的8位微控制器
文件页数: 82/110页
文件大小: 1685K
代理商: PSD8134V90JT
PSD813F1
82/110
Table 48. CPLD Combinatorial Timing (3V devices)
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.
2. ZPSD versions only.
Figure 43. Synchronous Clock Mode Timing
PLD
Symbol
Parameter
Conditions
-15
-20
PT
Aloc
Turbo
Off
2
Slew
rate
1
Unit
Min
Max
Min
Max
t
PD
CPLD Input Pin/Feedback
to CPLD Combinatorial
Output
48
55
+ 4
+ 20
6
ns
t
EA
CPLD Input to CPLD Output
Enable
43
50
+ 20
6
ns
t
ER
CPLD Input to CPLD Output
Disable
43
50
+ 20
6
ns
t
ARP
CPLD Register Clear or
Preset Delay
48
55
+ 20
6
ns
t
ARPW
CPLD Register Clear or
Preset Pulse Width
30
35
+ 20
ns
t
ARD
CPLD Array Delay
Any
macrocell
29
33
+ 4
ns
tCH
tCL
tCO
tH
tS
CLKIN
INPUT
REGISTERED
OUTPUT
AI02860
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