参数资料
型号: PSD813F3V-12
厂商: 意法半导体
英文描述: Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
中文描述: Flash在系统可编程(ISP)的周边8位MCU,5V的
文件页数: 31/110页
文件大小: 1685K
代理商: PSD813F3V-12
31/110
PSD813F1
MEMORY SELECT SIGNALS
The main Flash (FSi), EEPROM (EESi), and
SRAM (RS0) memory select signals are all out-
puts of the DPLD. They are setup by entering
equations for them in PSDsoft Express. The fol-
lowing rules apply to the equations for the internal
chip select signals:
1.
Flash memory and EEPROM sector select
signals must not be larger than the physical
sector size.
2.
Any main Flash memory sector must not be
mapped in the same memory space as
another Flash sector.
3.
An EEPROM sector must not be mapped in
the same memory space as another EEPROM
sector.
4.
SRAM, I/O, and Peripheral I/O spaces must
not overlap.
5.
An EEPROM sector may overlap a main Flash
memory sector. In case of overlap, priority will
be given to the EEPROM.
6.
SRAM, I/O, and Peripheral I/O spaces may
overlap any other memory sector. Priority will
be given to the SRAM, I/O, or Peripheral I/O.
Example
FS0 is valid when the address is in the range of
8000h to BFFFh, EES0 is valid from 8000h to
9FFFh, and RS0 is valid from 8000h to 87FFh.
Any address in the range of RS0 will always ac-
cess the SRAM. Any address in the range of EES0
greater than 87FFh (and less than 9FFFh) will au-
tomatically address EEPROM segment 0. Any ad-
dress greater than 9FFFh will access the Flash
memory segment 0. You can see that half of the
Flash memory segment 0 and one-fourth of EE-
PROM segment 0 can not be accessed in this ex-
ample. Also note that an equation that defined FS1
to anywhere in the range of 8000h to BFFFh would
not be valid.
Figure
11
shows the priority levels for all memory
components. Any component on a higher level can
overlap and has priority over any component on a
lower level.
Components on the same level must not overlap.
Level one has the highest priority and level 3 has
the lowest.
Memory Select Configuration for MCUs with
Separate Program and Data Spaces
The 8031 and compatible family of microcontrol-
lers, which includes the 80C51, 80C151, 80C251,
80C51XA, and the C500 family, have separate ad-
dress spaces for code memory (selected using
PSEN) and data memory (selected using RD). Any
of the memories within the PSD can reside in ei-
ther space or both spaces. This is controlled
through manipulation of the VM register that re-
sides in the PSD
s CSIOP space.
The VM register is set using PSDsoft Express to
have an initial value. It can subsequently be
changed by the microcontroller so that memory
mapping can be changed on-the-fly. For example,
I may wish to have SRAM and Flash in Data
Space at boot, and EEPROM in Program Space at
boot, and later swap EEPROM and Flash. This is
easily done with the VM register by using PSDsoft
Express to configure it for boot up and having the
microcontroller change it when desired. Table
12
describes the VM Register.
Figure 11. Priority Level of Memory and I/O
Components
Table 12. VM Register
Level 1
SRAM, I/O, or
Peripheral I/O
Level 2
Secondary
EEPROM Memory
Highest Priority
Lowest Priority
Level 3
Flash Memory
AI09221
Bit 7
PIO_EN
Bit 6
Bit 5
Bit 4
FL_Data
Bit 3
EE_Data
Bit 2
FL_Code
Bit 1
EE_Code
Bit 0
SRAM_Code
0 = disable
PIO mode
not used
not used
0 = RD can
t
access
Flash
memory
0 = RD can
t
access EEPROM
0 = PSEN
can
t access
Flash
memory
0 = PSEN can
t
access EEPROM
0 = PSEN
can
t access
SRAM
1= enable
PIO mode
not used
not used
1 = RD
access
Flash
memory
1 = RD access
EEPROM
1 = PSEN
access
Flash
memory
1 = PSEN
access EEPROM
1 = PSEN
access
SRAM
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