收藏本站
参数资料
型号： PSD834F2
英文描述： Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs(用于8位MCUs的闪速ISP外围)
中文描述： Flash在系统可编程（ISP）为周边8位微控制器（用于8位微控制器的闪速的ISP外围）
文件页数： 18/98页
文件大小： 595K
代理商： PSD834F2
PSD8XXF2/3/4/5
18/98
Erase or Program instruction is being executed by
the embedded algorithm. See the section entitled
“Programming Flash Memory”, on page 19, for de-
tails.
Table 9. Status Bit
Note: 1. X = Not guaranteed value, can be read either 1 or 0.
2. DQ7-DQ0 represent the Data Bus bits, D7-D0.
3. FS0-FS7 and CSBOOT0-CSBOOT3 are active High.
Data Polling Flag (DQ7).
When erasing or pro-
gramming in Flash memory, the Data Polling Flag
(DQ7) bit outputs the complement of the bit being
entered for programming/writing on the DQ7 bit.
Once the Program instruction or the Write opera-
tion is completed, the true logic value is read on
the Data Polling Flag (DQ7) bit (in a Read opera-
tion).
I
Data Polling is effective after the fourth Write
pulse (for a Program instruction) or after the
sixth Write pulse (for an Erase instruction). It
must be performed at the address being
programmed or at an address within the Flash
memory sector being erased.
I
During an Erase cycle, the Data Polling Flag
(DQ7) bit outputs a 0. After completion of the
cycle, the Data Polling Flag (DQ7) bit outputs
the last bit programmed(it is a 1 after erasing).
I
If the byte to be programmed is in a protected
Flash memory sector, the instruction is ignored.
I
If all theFlash memory sectors to be erased are
protected, the Data Polling Flag (DQ7) bit is
reset to 0 for about 100
μ
s, and then returns to
the previous addressed byte. No erasure is
performed.
Toggle Flag (DQ6).
The PSD8xxF2/3/4/5 offers
another way for determining when theFlash mem-
ory Program cycle is completed. During the inter-
nal Write operation and when either the FS0-FS7
or CSBOOT0-CSBOOT3 is true, the Toggle Flag
(DQ6) bit toggles from 0 to 1 and 1 to 0 on subse-
quent attempts to read any byte of the memory.
When the internal cycle is complete, the toggling
stops and thedata read on the Data Bus D0-D7 is
the addressed memory byte. The device is now
accessible for a new Read or Write operation. The
cycle is finished when two successive Reads yield
the same output data.
I
The Toggle Flag (DQ6) bit is effective after the
fourth Write pulse (for a Program instruction)or
after the sixth Write pulse (for an Erase
instruction).
I
If the byte to be programmed belongs to a
protected Flash memory sector, the instruction
is ignored.
I
If all the Flash memory sectors selected for
erasure areprotected,theToggle Flag(DQ6)bit
toggles to 0 for about 100
μ
sand then returnsto
the previous addressed byte.
Error Flag (DQ5).
During a normal Program or
Erase cycle, the Error Flag (DQ5) bit is to 0. This
bit is set to 1 when there is a failure during Flash
memory Byte Program, Sector Erase, or Bulk
Erase cycle.
In thecase of Flash memory programming, theEr-
ror Flag (DQ5)bit indicates theattempt to program
a Flashmemory bit from the programmed state, 0,
to the erased state, 1, which is not valid. The Error
Flag (DQ5)bit may also indicate a Time-out condi-
tion while attempting to program a byte.
In caseof an error ina Flashmemory Sector Erase
or ByteProgram cycle, the Flash memory sector in
which the error occurred or to which the pro-
grammed byte belongs must no longer be used.
Other Flash memory sectors may still be used.
The Error Flag (DQ5) bit is reset after a Reset
Flash instruction.
Erase Time-out Flag (DQ3).
The Erase
out Flag (DQ3) bit reflects the time-out period al-
lowed between two consecutive Sector Erase in-
structions. The Erase Time-out Flag (DQ3) bit is
reset to 0 after a Sector Erase cycle for a time pe-
riod of 100
μ
s + 20% unless an additional Sector
Erase instruction is decoded. After this time peri-
od, or when the additional Sector Erase instruction
is decoded, the Erase Time-out Flag (DQ3) bit is
set to 1.
Time-
Functional Block
FS0-FS7/CSBOOT0-
CSBOOT3
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
Flash Memory
V
IH
Data
Polling
Toggle
Flag
Error
Flag
X
Erase
Time-
out
X
X
X
相关PDF资料
PDF描述
PSD835G2 Configurable Memory System on a Chip for 8-Bit Microcontrollers(8位微控制器片上存储器可编程外设)
PSD835G2 100V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a TO-254AA Tabless package; Similar to IRHMJ57160 with optional Total Dose Rating of 1000kRads
PSD835G2V 150V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-2 package. Also available with 300 kRads Total Dose Rating.; Similar to IRHNA67164 with optional Total Dose Rating of 300 kRads.
PSD835G2-B-12B81 Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835F2-B-12B81 Configurable Memory System on a Chip for 8-Bit Microcontrollers
相关代理商/技术参数
参数描述
PSD834F2-15M 制造商:STMicroelectronics 功能描述:Flash In-System Programmable Peripherals 52-Pin PQFP
PSD834F2-70J 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 2M 70ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
PSD834F2-70M 功能描述:SPLD - 简单可编程逻辑器件 5.0V 2M 70ns RoHS:否 制造商:Texas Instruments 逻辑系列:TICPAL22V10Z 大电池数量:10 最大工作频率:66 MHz 延迟时间:25 ns 工作电源电压:4.75 V to 5.25 V 电源电流:100 uA 最大工作温度:+ 75 C 最小工作温度:0 C 安装风格:Through Hole 封装 / 箱体:DIP-24
PSD834F2-90J 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
PSD834F2-90JI 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*