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参数资料
型号： PSD853F2-15JIT
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 128K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52
封装： PLASTIC, LCC-52
文件页数： 64/103页
文件大小： 1180K
代理商： PSD853F2-15JIT
63/103
PSD8XXF2/3/4/5
RESET TIMING AND DEVICE STATUS AT RESET
Upon Power-up, the PSD8XXFX requires a Reset
(RESET) pulse of duration tNLNH-PO after VCC is
steady. During this period, the device loads inter-
nal configurations, clears some of the registers
and sets the Flash memory into Operating mode.
After the rising edge of Reset (RESET), the
PSD8XXFX remains in the Reset mode for an ad-
ditional period, tOPR, before the first memory ac-
cess is allowed.
The Flash memory is reset to the READ Mode
upon Power-up. Sector Select (FS0-FS7 and
CSBOOT0-CSBOOT3) must all be Low, Write
Strobe (WR, CNTL0) High, during Power On Re-
set for maximum security of the data contents and
to remove the possibility of a byte being written on
the first edge of Write Strobe (WR, CNTL0). Any
Flash memory WRITE cycle initiation is prevented
automatically when VCC is below VLKO.
Warm Reset
Once the device is up and running, the device can
be reset with a pulse of a much shorter duration,
tNLNH. The same tOPR period is needed before the
device is operational after warm reset. Figure 31
shows the timing of the Power-up and warm reset.
I/O Pin, Register and PLD Status at Reset
Table 33 shows the I/O pin, register and PLD sta-
tus during Power On Reset, warm reset and Pow-
er-down mode. PLD outputs are always valid
during warm reset, and they are valid in Power On
Reset once the internal PSD8XXFX Configuration
bits are loaded. This loading of PSD8XXFX is
completed typically long before the VCC ramps up
to operating level. Once the PLD is active, the
state of the outputs are determined by the PSDa-
bel equations.
Reset of Flash Memory Erase and Program
Cycles (on the PSD834Fx)
A Reset (RESET) also resets the internal Flash
memory state machine. During a Flash memory
Program or Erase cycle, Reset (RESET) termi-
nates the cycle and returns the Flash memory to
the Read Mode within a period of tNLNH-A.
Figure 31. Reset (RESET) Timing
tNLNH-PO
tOPR
AI02866b
RESET
tNLNH
tNLNH-A
tOPR
VCC
V
CC(min)
Power-On Reset
Warm Reset
相关PDF资料
PDF描述
PSD833F2-15M 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52
PSD835G2V-B-90MI Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835G2V-B-90U Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835G2V-B-90UI Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835G2V-C-12B81I Configurable Memory System on a Chip for 8-Bit Microcontrollers
相关代理商/技术参数
参数描述
PSD853F2-70J 功能描述:SPLD - 简单可编程逻辑器件 5.0V 1M 70ns RoHS:否 制造商:Texas Instruments 逻辑系列:TICPAL22V10Z 大电池数量:10 最大工作频率:66 MHz 延迟时间:25 ns 工作电源电压:4.75 V to 5.25 V 电源电流:100 uA 最大工作温度:+ 75 C 最小工作温度:0 C 安装风格:Through Hole 封装 / 箱体:DIP-24
PSD853F2-70M 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 1M 70ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
PSD853F2-90J 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
PSD853F2-90JI 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
PSD853F2-90M 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
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