参数资料
型号: PT7A6527
英文描述: 60V Single N-Channel Hi-Rel MOSFET in a TO-204AE package
中文描述: 四通道协议控制器? |演示板原理图和计划?(PDF格式)
文件页数: 39/41页
文件大小: 1640K
代理商: PT7A6527
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7
PT Pericom Technology Inc.
The Demo Board of PT7A6525
in DMA Mode
EPLD
A EPLD (Altera EPM7128S) is used in this demo board
to generate control signals. These signals include chip-
select signals, DMA control signals, control signals of
MC68HC000, and frequency-divided clock signals.
The schematics of the EPLD internal logic functions is
shown in Appendix B.
Power
There are three power ports on the demo board. +5V
VCC power should be provided through one of these
ports. When the power switch is on the “on” direction,
the power on the demo board is connected to the input
of the power port.
Jumpers
There are two groups of jumpers on the demo board.
Normally, these jumpers should be connected as shown
in Figure 1.
The Principle of PT7A6525 DMA In-
terface
This part includes the DMA transferring process of
PT7A6525 and the program flow of CPU to imple-
ment the transmitting or receiving process of a HDLC
frame.
The PT7A6525 works in DMA mode when the bit D7
of the register XBCH is set to “1”.
The DMA Transferring Process of
PT7A6525
When PT7A6525 works in DMA mode, the process of
transmitting/receiving a frame is simpler than in inter-
rupt request mode.
Before transmitting a frame, the data of the frame must
be stored in the system memory, and DMA controller
must be programmed. Because the XFIFO in
PT7A6525 is 32 bytes, a frame whose length is longer
than 32 bytes will be divided into several parts in trans-
ferring process. Figure 3 shows the process of
Frame Transmission in DMA Mode when the length
of frame is more than 32 bytes.
PT7A6525
(PT7A6526)
WR(N-1)
XTF
DRQT(32)
32 Bytes
CPU/DMA
Interface
DRQT(32)
32 Bytes
Serial
Output
32 Bytes
DRQT(N Mod 32)
N Mod 32 Bytes
XPR
Figure 3. Frame Transmission in DMA Mode
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