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参数资料
| 型号： | PT7A6527 |
| 英文描述： | 60V Single N-Channel Hi-Rel MOSFET in a TO-204AE package |
| 中文描述： | 四通道协议控制器？ |演示板原理图和计划？（PDF格式） |
| 文件页数： | 40/41页 |
| 文件大小： | 1640K |
| 代理商： | PT7A6527 |
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8
PT Pericom Technology Inc.
The Demo Board of PT7A6525
in DMA Mode
During the transmission of a frame of N bytes,
PT7A6525 will request the DMA controller to trans-
mit for N1 times by setting DRQT high, and N = (N1-
1)*32 + (N Mod 32). During the transmission of a block,
DRQT remains high and a byte of data is transferred
from system memory to PT7A6525 in every bus cycle
when DACK is active. When a block reading is fin-
ished, the DRQT goes low until the next request of
PT7A6525. After the frame is sent, PT7A6525 gener-
ates an interrupt to CPU and sets the XPR bit in ISTA
register. In this demo board, CPU doesn’t acknowledge
the interrupt. The Demo Program inquires the ISTA
register and decides the next operation.
In the Demo Program, the DMA channels of 8237 are
programmed to work in Demand mode. Thus 8237
checks the current status of DRQT and transfers the
correct byte count of data in each block transferring
process. When DRQT is inactive, 8237 discharges the
control of system bus and CPU is allowed to operated.
When PT7A6525 is receiving a frame, it requests the
DMA controller to transfer the data from RFIFO to
system memory after a 32-byte data block is received
or the frame is finished. Only after the reception of a
frame is finished, PT7A6525 generates a RME inter-
rupt to CPU. Before this interrupt, the receiving pro-
cess need not any control of CPU.
If the length of the frame is not definite, the maximum
of the frame length should be wrote to the Base Word
Count Register of the corresponding channel in 8237.
Thus it is assured that the total frame can be trans-
ferred to a successive area in system memory. As a ref-
erence, the maximum of the frame which PT7A6525
can transmit/receive in DMA mode is 4096. (In this
demo board, the length is less than 128.) After a frame
is received, CPU processes the data, and then sets
PT7A6525 and DMA controller to wait for the recep-
tion of the next frame.
Figure 4 shows the process of the Frame Reception in
DMA Mode when the length of frame is more than 32
bytes.
PT7A6525
(PT7A6526)
DRQR(32)
32 Bytes
CPU/DMA
Interface
DRQR(32)
32 Bytes
Serial
Input
32 Bytes
DRQR(N2)
N Mod 32 Bytes
RME
RD Count
RMC
Figure 4. Frame Reception in DMA Mode
During the reception of a frame of N bytes, PT7A6525
will request the DMA controller for N1 times by set-
ting DRQR high, and N = (N1-1)*32 + (N Mod 32).
Here, the last DRQR remains high during the transfer-
ring of N2 bytes. Table 1 shows N2 (the count of re-
quest bus cycles) and N Mod 32 (the count of the bytes
in RFIFO at the last DRQR).
Table 1. The bus cycles of the last DRQR
N Mod 32
N2
1 ~ 3
4
4 ~ 7
8
8 ~ 15
16
16 ~ 32
32
The DMA channels of 8237 are also programmed to
work in Demand mode.
After a reception, CPU may check the RME interrupt
of PT7A6525, read the count of the data, and send RMC
command to PT7A6525. CPU can also set the DMA
controller for the next reception.
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