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| 型号： | PTRF1221IRGZR |
| 厂商： | Texas Instruments |
| 文件页数： | 12/31页 |
| 文件大小： | 0K |
| 描述： | PTRF1221IRGZR |
| 产品培训模块： | RFID Technology and Applications |
| 标准包装： | 2,500 |
| 功能： | 升频器 |
| 频率： | 1.7GHz ~ 3.6GHz |
| RF 型： | UHF |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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TRF1121
TRF1221
SLWS170B – APRIL 2005 – REVISED JANUARY 2008
www.ti.com
INTEGRATED SYNTHESIZERS
PLL Programming
Synthesizer #1 (UHF) and synthesizer #2 (S-band) are both integrated in the TRF1121/TRF1221. These two
PLLs can be programmed via a 3-wire serial bus (CLK, DATA, and EN) from the baseband processor. The timing
specifications are given in the ac timing table .
Synthesizer #2 has a step size of 1 MHz, while Synthesizer #1 offers a step size of 50 kHz, both assuming an
18-MHz reference frequency. Different reference frequencies yield different step sizes, many of which may be
non-integer.
NOTE:
If left unconnected, the DATA, CLK and EN pins rest on logic-high. EN is
level-sensitive.
Data is written to the PLLs according to the format in Figure 8 .
MSB
Byte 1
LSB
MSB
Byte 2
LSB
MSB
Byte 3
LSB
Address
Data
A[7]
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
D[15]
D[14]
D[13]
D[12]
D[11]
D[10]
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
Synth #1 N divider
Synth #2 N divider
Synth #1 S counter
Synth #2 S counter
Synth #1 F counter
Synth #2 F counter
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
PS
0
0
0
0
0
0
0
0
all other addresses reserved for future expansion
Figure 8. Serial Interface Data Format
The first eight bits are the appropriate address for the instruction set and the remaining 16 bits are the
instructions. The data is 24 bits long (3 bytes). Byte 1 is the address with A[7] being the MSB and A[0] being the
LSB. Byte 2 and 3 program the IC with synthesizer information and PS (Polarity Select Bit) information. D[15] is
the MSB and D[8] the LSB. The PS bit selects which edge of the reference is used for frequency comparison.
Improved spurious and phase noise is achieved by selecting the edge with the fastest rise or fall time. If PS = 1
the rising edge is used as the reference. If PS = 0, the falling edge is used.
The data of Figure 8 must be sent to the TRF1121 / TRF1221 to fully program synthesizers #1 and #2 and the
PS bit. Once the synthesizers and the PS bit are fully programmed, the clock signal should be turned off to
eliminate any clock-related spurious signals.
The LO1 (UHF oscillator) frequency of oscillation is set by Equation 1 :
f out = REFIN ′ ê 8 ′ (N + 3) - S -
é
?
F ù
18 ú ?
? é ? 2 ′ M ù ?
(1)
where:
F = synthesizer F counter
M = 10 for TRF1121 and 8 for 1221
N = synthesizer N divider
S = synthesizer S counter (see Figure 8 )
12
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Copyright ? 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): TRF1121 TRF1221
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