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参数资料
| 型号： | PTV05010WAH |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 电源模块 |
| 英文描述： | 1-OUTPUT DC-DC REG PWR SUPPLY MODULE |
| 封装： | SIP-8 |
| 文件页数： | 13/19页 |
| 文件大小： | 462K |
| 代理商： | PTV05010WAH |
www.ti.com
ELECTRICAL CHARACTERISTICS
SLTS242A – FEBRUARY 2005 – REVISED OCTOBER 2005
operating at 25
°C free-air temperature, V
I = 5 V, VO = 3.3 V, C1 = 100 F, C2 = 10 F, C3 = 0 F, C4 = 0 F, and IO = IO max
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IO
Output current
Natural convection airflow
0
8 (1)
A
VI
Input voltage range
Over IO load range
4.5
5.5
V
Set-point voltage tolerance
2% (2)
Temperature variation
–40
°C < T
A < 85°C
0.5%
Line regulation
Over VI range
5
mV
VO
Load regulation
Over IO range
5
mV
Total output variation
Includes set-point, line, load, –40
°C ≤ T
A ≤ 85°C
3 (2)
%Vo
Adjust range
Over VI range
0.8
3.6
V
RSET = 698 , VO = 3.3 V
95%
RSET = 2.21 k, VO = 2.5 V
93%
RSET = 5.49 k, VO = 1.8 V
90%
η
Efficiency
IO = IO max
RSET = 8.87 k, VO = 1.5 V
89%
RSET = 17.4 k, VO = 1.2 V
87%
RSET = 36.5 k, VO = 1 V
85%
Output voltage ripple (pk-pk)
20-MHz bandwidth
15
mVPP
IO (trip)
Overcurrent threshold
Reset, followed by auto-recovery
12
A
1-A/
s load step, 50 to 100% I
O max, C3 = 100 F
Transient response
Recovery time
70
s
Vo over/undershoot
100
mV
IIL Input low current
Pin to GND
–0.13
mA
Track control (pin 9)
Control slew-rate limit
C3
≤ C3 (max)
1
V/ms
VI increasing
4.3
4.5
UVLO
Undervoltage lockout
V
VI decreasing
3.1
3.7
VIH Input high voltage
VI – 0.5
Open (3)
Referenced to GND
V
Inhibit control (pin 12)
VIL Input low voltage
–0.2
0.6
IIL Input low current
Pin to GND
0.24
mA
II (stby)
Input standby current
Inhibit (pin 7) to GND, Track (pin 5) open
5
mA
S
Switching frequency
Over VI and IO ranges
550
600
650
kHz
Nonceramic (C1)
100 (4)
External input capacitance
F
Ceramic (C2)
10 (4)
Nonceramic
0
100 (5)
3300 (6)
Capacitance value
F
External output capacitance (C3)
Ceramic
0
300
Equivalent series resistance (nonceramic)
4 (7)
m
Per Telcordia SR-332, 50% stress, TA = 40°C, ground
MTBF
Reliability
5
106 Hr
benign
(1)
See thermal derating curves for safe operating area (SOA), or consult factory for appropriate derating.
(2)
The set-point voltage tolerance is affected by the tolerance and stability of RSET. The stated limit is unconditionally met if RSET has a
tolerance of 1%, with 100 ppm/
°C or better temperature stability.
(3)
This control pin is internally pulled up to the input voltage, VI. If this input is left open circuit, the module will operate when input power is
applied. A small low-leakage (< 100 nA) MOSFET is recommended for control. For further information, see the related application note.
(4)
A 10-
F high-frequency ceramic capacitor and 100-F electrolytic input capacitor are required for proper operation. The electrolytic
capacitor must be rated for 300 mArms minimum ripple current. See the Application Information for further guidance on capacitor
selection.
(5)
An external output capacitor is not required for basic operation. Adding 100
F of distributed capacitance at the load improves the
transient response.
(6)
This is the calculated maximum. The minimum ESR limitation often results in a lower value. When controlling the Track pin using a
voltage supervisor, CO(max) is reduced to 2200 F. See the Application Information for further guidance.
(7)
This is the typical ESR for all the electrolytic (nonceramic) output capacitance. Use 7 m
as the minimum when using maximum-ESR
values to calculate.
Copyright 2005, Texas Instruments Incorporated
3
Product Folder Link(s) :PTV05010W
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