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参数资料
| 型号： | PUMA2S1000M-35 |
| 元件分类： | SRAM |
| 英文描述： | 32K X 32 MULTI DEVICE SRAM MODULE, 35 ns, CPGA66 |
| 封装： | CERAMIC, PGA-66 |
| 文件页数： | 3/9页 |
| 文件大小： | 240K |
| 代理商： | PUMA2S1000M-35 |
PUMA 2S1000 - 25/35/45
ISSUE 4.3 : November 1998
3
1 = V
IH,0 = VIL,
X = Don't Care
Note: CS is accessed through CS1~4, and WE is accessed through WE1~4. For correct operation, CS1~4 must
operate simultaneously for 32 bit operation, in pairs for 16 bit operation, or singly for 8 bit operation. WE1~4
must also be operated in the same manner.
Mode
CS
OE
WE
V
CC Current
I/O Pin Reference Cycle
Not Selected
1
X
I
SB,ISB1,ISB2
High Z
Power Down
OutputDisable
0
1
I
CC
High Z
Read
0
1
I
CC
D
OUT
Read Cycle
Write
0
X
0
I
CC
D
IN
Write Cycle
Operating Modes
The Table below shows the logic inputs required to control the operating modes of each of the SRAMs on the
PUMA 2S1000.
Low V
cc Data Retention Characteristics - L Version Only (VCC = 5.0V±10%, TA=-55°C to +125°C)
Parameter
Symbol
Test Condition
min
typ
max
Unit
V
CC for Data Retention
V
DR
CS
≥V
CC-0.2V, VIN≥0V
2.0
-
5.5
V
Data Retention Current
I
CCDR1
V
CC=2.0V, CS≥VCC-0.2V, VIN≥0V
--
8
mA
-L Version
I
CCDR2
As above
-
1.2
mA
Chip Deselect to Data Retention Time
t
CDR
See Retention Waveform
0-
-
ns
Operation Recovery Time
t
R
See Retention Waveform
t
RC
--
ns
AC Test Conditions
Output Load
* Input pulse levels: 0V to 3.0V
* Input rise and fall times: 3ns
* Input and Output timing reference levels: 1.5V
* Output load: see diagram
* V
cc=5V±10%
166
30pF
I/O Pin
1.76V
Note: CS above is accessed through CS1~4.
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相关代理商/技术参数 |
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