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参数资料
| 型号： | PUMA68F4001MB-15 |
| 元件分类： | PROM |
| 英文描述： | 128K X 32 FLASH 5V PROM MODULE, 150 ns, PQMA68 |
| 封装： | PLASTIC, LCC-68 |
| 文件页数： | 10/12页 |
| 文件大小： | 495K |
| 代理商： | PUMA68F4001MB-15 |
PUMA 68F4001-15/17/20
ISSUE 4.1 : AUGUST 1997
7
Device Operation
Read
The PUMA 68F4001 read operations are initiated when Write Enable is high and both Output Enable and Chip
Select are LOW. The read operation is terminated by either Chip Select or Output Enable returning HIGH. This
2-line control architecture eliminates bus connection in a system environment. The data bus will be in a high
impedance state when either Output Enable or Chip Select is HIGH.
Write
The device is reprogrammed on a sector basis. Byte loads are used to enter the 128 bytes of a sector to be
programmed or the software codes for data protection. A byte load is performed by applying a low pulse on the WE
or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE,
whichever occurs last. The data is latched by the first rising edge of CE or WE.
If a byte of data within a sector is to be changed, data for the entire sector must be loaded into the device. Any byte
that is not loaded during the programming of its sector will be erased to read FFh.
During a reprogram cycle, the address locations and 128 bytes of data are internally latched, freeing the address
and data bus for other operations. Following the initiation of a program cycle, the device will automatically erase
the sector and then program the latched data using an internal control timer. The end of a program cycle can be
detected by DATA polling on D7. Once the end of a program cycle has been detected, a new access for a read
or program can begin.
Each new byte to be programmed must have its high to low transition on WE (or CE) within 150s of the high
to low transition of WE (or CE) of the preceding byte. If a high to low transition is not detected within 150 s of
the last low to high transition, the load period will end and the internal programming period will start. A7 to A16
specify the sector address. The sector address must be valid during each high to low transition of WE (or CE).
A0 to A6 specify the byte address within the sector. The bytes may be loaded in any order; sequential loading
is not required.
DATA Polling
In order to detect the end of a write cycle, two methods are provided. During a write operation (Byte or Page)
an attempt to read the last byte written will result in the compliment of the written data appearing on D7 (or
D15, D23 or D31, depending on the device selected). Once the write cycle is completed, true data appears on
the outputs and the next write cycle may begin. Using this method of indicating the end of a write can
effectively reduce the total write time by 50%.
TOGGLE bit
In addition to DATA polling, another method is provided to determine the end of a Write Cycle. During a write
operation successive attempts to read data will result in D6 (or D14, D22 or D30, depending on the device selected).
toggling between 1 and 0. Once a write is complete, this toggling will stop and valid data will be read as normal,
allowing the next write cycle to be performed. This can eliminate the software housekeeping chore of saving and
fetching the last address and data written in order to implement DATA polling. This can be especially helpful in
an array composed of multiple PUMA 68F4001 modules that are frequently updated.
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相关代理商/技术参数 |
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|---|---|
| PUMA68F4001MB-17 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x32 Flash EEPROM Module |
| PUMA68F4001MB-20 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x32 Flash EEPROM Module |
| PUMA68F4003-12 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x32 Flash EEPROM Module |
| PUMA68F4003-15 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x32 Flash EEPROM Module |
| PUMA68F4003-20 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x32 Flash EEPROM Module |
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