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参数资料
| 型号： | PW-82351-120 |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 运动控制电子 |
| 英文描述： | BRUSHLESS DC MOTOR CONTROLLER, 150 A, XMA |
| 文件页数： | 13/16页 |
| 文件大小： | 273K |
| 代理商： | PW-82351-120 |
6
FIGURE 3. UMC DELAY CIRCUIT
FIG 3A. UMC TIED LOW
FIG 3B. UMC CONTROLLED BY EXTERNAL CIRCUIT
UNDER VOLTAGE FLAG (UV FLAG)
There are two conditions which will cause the UV FLAG to be
set. The UV FLAG output will go low (logic 0) when the +5V
and/or the +15V power supply inputs to the PW-82351 drop
below the internally set low supply levels. The nominal under-
voltage levels are +4.35V for the +5V supply and +13V for the
+15V supply. The -15V supply has no effect on the UV FLAG
signal. The UV FLAG will also go low when the UMC input is a
logic 1 (disabled).
TWO-QUADRANT OR FOUR-QUADRANT (2Q - 4Q)
A logic ‘1’ on this input will select the Two-Quadrant modulation
mode. When operating in the Two-Quadrant mode, the PWM
signal is applied to the upper output transistor while the com-
mutation signal is applied to the lower output transistor of the
different phase. A logic ‘0’ at the input will select the Four-
Quadrant modulation mode. Operation in the Four-Quadrant
mode is the same as the Two-Quadrant except that the PWM
signal is applied to the upper transistor and a complementary
signal is applied to the lower transistor in the same phase,
while the commutation signal is applied to the lower transistor
of the different phase.
DISABLE / ENABLE (DIS/EN)
The DISABLE / ENABLE input will shut down the output stage
when in the disable mode, logic high (1). The input is internally
pulled high and must be tied to a logic low (0) in order to be
enabled. When disabled, switching on the logic inputs will not
switch the output transistors, see TABLE 4. When redundant
shutdown of the output transistors are required, the disable
input and the UMC input can be used.
INPUT SEL
The input select pin (INPUT SEL) controls the dual function
logic inputs. As shown in TABLE 5, a logic ‘1’ enables the inter-
nal commutation logic for operation in the self commutated
mode. A logic ‘0’ enables the six parallel inputs for individual
output transistor control. The input select pin is a logic high
input.
TABLE 5. DUAL FUNCTION INPUTS
INPUT SEL
FUNCTION
ACTIVE INPUT PINS
1
Internal Commutation
Logic
DIR, PWM, BRAKE, IDIR,
2Q-4Q, BRAKE PWM,
0
Six Parallel Inputs
UA, LA, UB, LB, UC, LC
PW-82351
+5 V
33K
1N4148
R
1K
C
UMC
J2-6
+5 V
UMC
DRIVING
CIRCUIT
+5 V
33K
+5 V
UMC
1N4148
R 1K
C
PW-82351
TABLE 6. PW-82351P6
COMMUTATION TRUTH TABLE (USING INTERNAL COMMUTATION LOGIC)
CONTROLS
INPUTS
HALLS
OUTPUTS
UMC
INPUT
SEL
DISABLE /
ENABLE
DIR
BRAKE
ICONTROL
BRAKE
PWM
HA
HB
HC
PHASE
A OUT
PHASE
B OUT
PHASE
C OUT
0
1
0
1
0
X
0
1
L
Z
H
0
1
0
1
0
X
0
1
0
L
H
Z
0
1
0
1
0
X
1
0
Z
H
L
0
1
0
1
0
X
1
0
H
Z
L
0
1
0
1
0
X
1
0
1
H
L
Z
0
1
0
1
0
X
0
1
Z
L
H
0
1
0
X
1
0
Z
L
H
0
1
0
X
0
1
0
H
L
Z
0
1
0
X
0
1
H
Z
L
0
1
0
X
0
1
Z
H
L
0
1
0
X
1
0
1
L
H
Z
0
1
0
X
1
0
L
Z
H
0
1
0
X
1
0
1
X
L
0
1
0
X
1
0
X
Z
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