参数资料
型号: PW-82520N0-170
厂商: DATA DEVICE CORP
元件分类: 运动控制电子
英文描述: BRUSHLESS DC MOTOR CONTROLLER, 18 A, DMA41
封装: HYBRID, DIP-41
文件页数: 4/13页
文件大小: 773K
代理商: PW-82520N0-170
R8C/3JC Group
2. Central Processing Unit (CPU)
REJ03B0302-0100 Rev.1.00
Page 12 of 54
May 25, 2010
2.1
Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split
into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are
analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is
analogous to R2R0.
2.2
Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also
used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32-
bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the starting address of an interrupt vector table.
2.5
Program Counter (PC)
PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP and ISP, are each 16 bits wide. The U flag of FLG is used to switch between
USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8
Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1
Carry Flag (C)
The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.
2.8.2
Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3
Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4
Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.
2.8.5
Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6
Overflow Flag (O)
The O flag is set to 1 when an operation results in an overflow; otherwise to 0.
相关PDF资料
PDF描述
PW-82520N0-450 BRUSHLESS DC MOTOR CONTROLLER, 18 A, DMA41
PW-82520N1-110 BRUSHLESS DC MOTOR CONTROLLER, 3 A, DMA41
PW-82520N1-550 BRUSHLESS DC MOTOR CONTROLLER, 3 A, DMA41
PW-82520N3-330 BRUSHLESS DC MOTOR CONTROLLER, 8 A, DMA41
PW-82521N0-390 BRUSHLESS DC MOTOR CONTROLLER, 18 A, DMA41
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