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| 型号： | PW-82520N0-170 |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 运动控制电子 |
| 英文描述： | BRUSHLESS DC MOTOR CONTROLLER, 18 A, DMA41 |
| 封装： | HYBRID, DIP-41 |
| 文件页数： | 5/13页 |
| 文件大小： | 773K |
| 代理商： | PW-82520N0-170 |
R8C/3JC Group
2. Central Processing Unit (CPU)
REJ03B0302-0100 Rev.1.00
Page 13 of 54
May 25, 2010
2.8.7
Interrupt Enable Flag (I)
The I flag enables maskable interrupts.
Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0
when an interrupt request is acknowledged.
2.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10
Reserved Bit
If necessary, set to 0. When read, the content is undefined.
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