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参数资料
| 型号： | PX3511ADAG |
| 厂商： | Intersil |
| 文件页数： | 5/10页 |
| 文件大小： | 0K |
| 描述： | IC DRVR SYNC BUCK HF 8-SOIC |
| 标准包装： | 980 |
| 配置： | 高端和低端，同步 |
| 输入类型： | PWM |
| 延迟时间： | 10ns |
| 电流 - 峰： | 1.25A |
| 配置数： | 1 |
| 输出数： | 2 |
| 高端电压 - 最大（自引导启动）： | 36V |
| 电源电压： | 10.8 V ~ 13.2 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 管件 |
PX3511A, PX3511B
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Three-State Upper Gate Falling Threshold
Shutdown Holdoff Time
t TSSHD
VCC = 12V
-
-
1.96
245
-
-
V
ns
UGATE Rise Time
LGATE Rise Time
UGATE Fall Time (Note 4)
LGATE Fall Time (Note 4)
UGATE Turn-On Propagation Delay (Note 4)
LGATE Turn-On Propagation Delay (Note 4)
UGATE Turn-Off Propagation Delay (Note 4)
LGATE Turn-Off Propagation Delay (Note 4)
LG/UG Three-State Propagation Delay (Note 4)
t RU
t RL
t FU
t FL
t PDHU
t PDHL
t PDLU
t PDLL
t PDTS
V PVCC = 12V, 3nF Load, 10% to 90%
V PVCC = 12V, 3nF Load, 10% to 90%
V PVCC = 12V, 3nF Load, 90% to 10%
V PVCC = 12V, 3nF Load, 90% to 10%
V PVCC = 12V, 3nF Load, Adaptive
V PVCC = 12V, 3nF Load, Adaptive
V PVCC = 12V, 3nF Load
V PVCC = 12V, 3nF Load
V PVCC = 12V, 3nF Load
-
-
-
-
-
-
-
-
-
26
18
18
12
10
10
10
10
10
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
OUTPUT
Upper Drive Source Current (Note 4)
Upper Drive Source Impedance
I U_SOURCE V PVCC = 12V, 3nF Load
R U_SOURCE 150mA Source Current
-
1.4
1.25
2.0
-
3.0
A
Ω
Upper Drive Sink Current (Note 4)
Upper Drive Sink Impedance
Lower Drive Source Current (Note 4)
I U_SINK
R U_SINK
I L_SOURCE
V PVCC = 12V, 3nF Load
150mA Sink Current
V PVCC = 12V, 3nF Load
-
0.9
-
2
1.65
2
-
3.0
-
A
Ω
A
Lower Drive Source Impedance
R L_SOURCE 150mA Source Current
0.85
1.3
2.2
Ω
Lower Drive Sink Current (Note 4)
Lower Drive Sink Impedance
I L_SINK
R L_SINK
V PVCC = 12V, 3nF Load
150mA Sink Current
-
0.60
3
0.94
-
1.35
A
Ω
NOTE:
4. Guaranteed by design. Not 100% tested in production.
Functional Pin Description
PACKAGE PIN #
PIN
SOIC
1
2
DFN
1
2
SYMBOL
UGATE
BOOT
FUNCTION
Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.
Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the Internal Bootstrap
Device section under DESCRIPTION for guidance in choosing the capacitor value.
-
3
3,8
4
N/C
PWM
No Connection.
The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation, see
the three-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM output of the
controller.
4
5
6
7
5
6
7
9
GND
LGATE
VCC
PVCC
Bias and reference ground. All signals are referenced to this node. It is also the power ground return of the driver.
Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
Connect this pin to a +12V bias supply. Place a high quality low ESR ceramic capacitor from this pin to GND.
This pin supplies power to both upper and lower gate drives in PX3511B; only the lower gate drive in PX3511A.
Its operating range is +5V to 12V. Place a high quality low ESR ceramic capacitor from this pin to GND.
8
10
PHASE
Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides
a return path for the upper gate drive.
9
11
PAD
Connect this pad to the power ground plane (GND) via thermally enhanced connection.
5
FN6462.0
February 26, 2007
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