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参数资料
| 型号： | PXA255 |
| 厂商： | Intel Corp. |
| 英文描述： | PXA255 Processor |
| 中文描述： | PXA255处理器 |
| 文件页数： | 15/40页 |
| 文件大小： | 1191K |
| 代理商： | PXA255 |
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Package Information
Intel PXA255 Processor
Electrical, Mechanical, and Thermal Specification
15
AC97 Controller and I
2
S Controller Pins
BITCLK/
GPIO[28]
ICOCZ
AC97 audio port bit clock.
(input) AC97 clock is
generated by Codec 0 and fed into the PXA255
processor processor and Codec 1.
AC97 Aaudio port bit clock.
(output) AC97 clock is
generated by the PXA255 processor.
I
2
S bit clock.
(input) I
2
S clock is generated externally
and fed into PXA255 processor.
I
2
S bit clock.
(output) I
2
S clock is generated by the
PXA255 processor.
Pulled High -
Note[1]
Note [3]
SDATA_IN0/
GPIO[29]
ICOCZ
AC97 audio port data in.
(input) Input line for Codec 0.
I
2
S data in.
(input) Input line for the I
2
S controller.
Pulled High -
Note[1]
Note [3]
SDATA_IN1/
GPIO[32]
ICOCZ
AC97 audio port data in.
(input) Input line for Codec 1.
I
2
S system clock.
(output) System clock from I
2
S
controller.
Pulled High -
Note[1]
Note [3]
SDATA_OUT/
GPIO[30]
ICOCZ
AC97 audio port data out.
(output) Output from the
PXA255 processor to Codecs 0 and 1.
I
2
S data out.
(output) Output line for the I
2
S controller.
Pulled High -
Note[1]
Note [3]
SYNC/
GPIO[31]
ICOCZ
AC97 audio port sync signal.
(output) Frame sync
signal for the AC97 controller.
I
2
S
sync.
(output) Frame sync signal for the I
2
S
controller.
Pulled High -
Note[1]
Note [3]
nACRESET
OC
AC97 audio port reset signal.
(output)
Driven Low
Driven Low
I
2
C Controller Pins
SCL
ICOCZ
I
2
C clock.
(bidirectional)
Hi-Z
Hi-Z
SDA
ICOCZ
I
2
C data.
(bidirectional).
Hi-Z
Hi-Z
PWM Pins
PWM[1:0]/
GPIO[17:16]
ICOCZ
Pulse width modulation channels 0 and 1.
(outputs)
Pulled High -
Note[1]
Note [3]
DMA Pins
DREQ[1:0]/
GPIO[19:20]
ICOCZ
DMA request.
(input) Notifies the DMA Controller that an
external device requires a DMA transaction. DREQ[1] is
GPIO[19]. DREQ[0] is GPIO[20].
Pulled High -
Note[1]
Note [3]
GPIO Pins
GPIO[1:0]
ICOCZ
General purpose I/O.
Wakeup sources on both rising
and falling edges on nRESET.
Pulled High -
Note[1]
Note [3]
GPIO[14:2]
ICOCZ
General purpose I/O.
More wakeup sources for sleep
mode.
Pulled High -
Note[1]
Note [3]
GPIO[22:21]
ICOCZ
General purpose I/O.
Additional General Purpose I/O
pins.
Pulled High -
Note[1]
Note [3]
Crystal and Clock Pins
PXTAL
OA
3.6864 MHz crystal input.
No external caps are
required.
Note [2]
Note [2]
PEXTAL
IA
3.6864 MHz crystal output.
No external caps are
required.
Note [2]
Note [2]
TXTAL
OA
32 KHz crystal input.
No external caps are required.
Note [2]
Note [2]
Table 3. Pin and Signal Descriptions for the PXA255 Processor (Sheet 7 of 9)
Pin Name
Type
Signal Descriptions
Reset State
Sleep State
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相关代理商/技术参数 |
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| PXA25VC22RMH70TP | 制造商:United Chemi-Con Inc 功能描述:Cap Aluminum 22uF 25V 20% (8 X 6.7mm) SMD 0.05 Ohm 1800mA 2000 hr 105°C T/R |
| PXA270 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:Electrical, Mechanical, and Thermal Specification |
| PXA300 | 制造商:Marvell 功能描述: |
| PXA310 | 制造商:MARVELL 制造商全称:MARVELL 功能描述:Rich Multimedia with Scalable Performance up to 624 MHz for Cost-Effective and Power-Effi cient Secure 3.5G Smartphones |
| PXA320 | 制造商:MARVELL 制造商全称:MARVELL 功能描述:Cost-Effective, Scalable Performance up to 806 MHz for Power-Efficient, High-End Multimedia Handsets, Embedded Solutions, and Enterprise-Class Devices |
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