- 您现在的位置：买卖IC网 > PDF目录370028 > PXA255 (Intel Corp.) PXA255 Processor PDF资料下载
参数资料
| 型号： | PXA255 |
| 厂商： | Intel Corp. |
| 英文描述： | PXA255 Processor |
| 中文描述： | PXA255处理器 |
| 文件页数： | 9/40页 |
| 文件大小： | 1191K |
| 代理商： | PXA255 |
第1页第2页第3页第4页第5页第6页第7页第8页当前第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页
Package Information
Intel PXA255 Processor
Electrical, Mechanical, and Thermal Specification
9
Some of the processor pins can be connected to multiple signals. The GAFRn_m registers
determine the signal connected to the pin. Some signals can go to multiple pins. The signal must be
routed to one pin only by using the GAFRn_m registers. Because this is true, some pins are listed
twice—once in each unit that can use the pin. Not all peripherals can be used simutaneously in one
design because different peripherals share the same pins.
Table 2. Processor Pin Types
Type
Function
IC
CMOS input
OC
CMOS output
OCZ
CMOS output, Hi-Z
ICOCZ
CMOS bidirectional, Hi-Z
IA
Analog Input
OA
Analog output
IAOA
Analog bidirectional
SUP
Supply pin (either VCC or VSS)
Table 3. Pin and Signal Descriptions for the PXA255 Processor (Sheet 1 of 9)
Pin Name
Type
Signal Descriptions
Reset State
Sleep State
Memory Controller Pins
MA[25:0]
OCZ
Memory address bus.
(output) Signals the address
requested for memory accesses.
Driven Low
Driven Low
MD[15:0]
ICOCZ
Memory data bus.
(input/output) Lower 16 bits of the
data bus.
Hi-Z
Driven Low
MD[31:16]
ICOCZ
Memory data bus.
(input/output) Used for 32-bit
memories.
Hi-Z
Driven Low
nOE
OCZ
Memory output enable.
(output) Connect to the output
enables of memory devices to control data bus drivers.
Driven High
Note [4]
nWE
OCZ
Memory write enable.
(output) Connect to the write
enables of memory devices.
Driven High
Note [4]
nSDCS[3:0]
OCZ
SDRAM CS for banks 3 through 0.
(output) Connect to
the chip select (CS) pins for SDRAM. For the PXA255
processor processor nSDCS0 can be Hi-Z, nSDCS1-3
cannot.
Driven High
Note [5]
DQM[3:0]
OCZ
SDRAM DQM for data bytes 3 through 0.
(output)
Connect to the data output mask enables (DQM) for
SDRAM.
Driven Low
Driven Low
nSDRAS
OCZ
SDRAM RAS.
(output) Connect to the row address
strobe (RAS) pins for all banks of SDRAM.
Driven High
Driven High
nSDCAS
OCZ
SDRAM CAS.
(output) Connect to the column address
strobe (CAS) pins for all banks of SDRAM.
Driven High
Driven High
SDCKE[0]
OC
Synchronous Static Memory clock enable.
(output)
Connect to the CKE pins of SMROM. The memory
controller provides control register bits for de-assertion.
Driven Low
Driven Low
相关PDF资料 |
PDF描述 |
|---|---|
| PXA270 | Electrical, Mechanical, and Thermal Specification |
| PXAC37 | XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-proce |
| PXB16050U | NPN microwave power transistor |
| PY08-02 | INDUSTRIERELAIS FASSUNG PCB |
| PY08-02186697 | SOCKET PCB |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PXA25VC22RMH70TP | 制造商:United Chemi-Con Inc 功能描述:Cap Aluminum 22uF 25V 20% (8 X 6.7mm) SMD 0.05 Ohm 1800mA 2000 hr 105°C T/R |
| PXA270 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:Electrical, Mechanical, and Thermal Specification |
| PXA300 | 制造商:Marvell 功能描述: |
| PXA310 | 制造商:MARVELL 制造商全称:MARVELL 功能描述:Rich Multimedia with Scalable Performance up to 624 MHz for Cost-Effective and Power-Effi cient Secure 3.5G Smartphones |
| PXA320 | 制造商:MARVELL 制造商全称:MARVELL 功能描述:Cost-Effective, Scalable Performance up to 806 MHz for Power-Efficient, High-End Multimedia Handsets, Embedded Solutions, and Enterprise-Class Devices |
发布紧急采购，3分钟左右您将得到回复。