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参数资料
| 型号： | PZ5128-S10BE-S |
| 英文描述： | Electrically-Erasable Complex PLD |
| 中文描述： | 电可擦除复杂可编程逻辑器件 |
| 文件页数： | 11/22页 |
| 文件大小： | 180K |
| 代理商： | PZ5128-S10BE-S |
Philips Semiconductors
Product specification
PZ5128
128 macrocell CPLD
1997 Aug 12
11
DC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL GRADE DEVICES
Commercial: 0
°
C
≤
T
amb
≤
+70
°
C; 4.75V
≤
V
DD
≤
5.25V
SYMBOL
PARAMETER
V
IL
Input voltage low
V
IH
Input voltage high
V
I
Input clamp voltage
V
OL
Output voltage low
V
OH
Output voltage high
I
I
Input leakage current
I
OZ
3-Stated output leakage current
I
DDQ
Standby current
TEST CONDITIONS
V
DD
= 4.75V
V
DD
= 5.25V
V
DD
= 4.75V, I
IN
= –18mA
V
DD
= 4.75V, I
OL
= 12mA
V
DD
= 4.75V, I
OH
= –12mA
V
IN
= 0 to V
DD
V
IN
= 0 to V
DD
V
DD
= 5.25V, T
amb
= 0
°
C
V
DD
= 5.25V, T
amb
= 0
°
C @ 1MHz
V
DD
= 5.25V, T
amb
= 0
°
C @ 50MHz
1 pin at a time for no longer than 1 second
T
amb
= 25
°
C, f = 1MHz
T
amb
= 25
°
C, f = 1MHz
T
amb
= 25
°
C, f = 1MHz
MIN.
MAX.
0.8
UNIT
V
V
V
V
V
μ
A
μ
A
μ
A
mA
2.0
–1.2
0.5
2.4
–10
–10
10
10
100
5
I
DDD1
Dynamic current
75
–200
8
12
10
mA
mA
pF
pF
pF
I
OS
C
IN
C
CLK
C
I/O
Short circuit output current
2
Input pin capacitance
2
Clock input capacitance
2
I/O pin capacitance
2
–50
5
NOTES:
1. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs disabled and unloaded.
Inputs are tied to V
DD
or ground. This parameter guaranteed by design and characterization, not testing.
2. Typical values, not tested.
AC ELECTRICAL CHARACTERISTICS
1
FOR COMMERCIAL GRADE DEVICES
Commercial: 0
°
C
≤
T
amb
≤
+70
°
C; 4.75V
≤
V
DD
≤
5.25V
SYMBOL
PARAMETER
–7
–10
–12
UNI
T
MIN/
2
MAX.
7.5
MIN.
2
MAX.
10
MIN.
2
MAX.
12
t
PD_PAL
Propagation delay time, input (or feedback node) to output through PAL
Propagation delay time, input (or feedback node) to output through PAL
& PLA
Clock to out delay time
Setup time (from input or feedback node) through PAL
Setup time (from input or feedback node) through PAL + PLA
Hold time
Clock High time
Clock Low time
Input Rise time
Input Fall time
Maximum FF toggle rate
2
1/(t
CH
+ t
CL
)
Maximum internal frequency
2
1/(t
SUPAL
+ t
CF
)
Maximum external frequency
2
1/(t
SUPAL
+ t
CO
)
Output buffer delay time
Input (or feedback node) to internal feedback node delay time through
PAL
Input (or feedback node) to internal feedback node delay time through
PAL+PLA
Clock to internal feedback node delay time
Delay from valid V
DD
to valid reset
Input to output disable
3
Input to output valid
Input to register preset
Input to register reset
ns
t
PD_PLA
3
9.5
3
12
3
14.5
ns
t
CO
t
SU_PAL
t
SU_PLA
t
H
t
CH
t
CL
t
R
t
F
f
MAX1
f
MAX2
f
MAX3
t
BUF
t
PDF_PA
L
t
PDF_PL
A
t
CF
t
INIT
t
ER
t
EA
t
RP
t
RR
NOTES:
2
6
2
7
9
7
2
8
8
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
4.5
6.5
10.5
0
0
0
3
3
4
4
4
4
20
20
20
20
20
20
167
111
95
125
80
71
125
69
63
1.5
1.5
1.5
2
6
2
8.5
2
10.5
ns
3
8
3
10.5
3
13
ns
4.5
50
9
9
11
11
5.5
50
12
12
12.5
12.5
6.5
50
15
15
15
15
ns
μ
s
ns
ns
ns
ns
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