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| 型号： | PZ5128-S10BE-S |
| 英文描述： | Electrically-Erasable Complex PLD |
| 中文描述： | 电可擦除复杂可编程逻辑器件 |
| 文件页数： | 8/22页 |
| 文件大小： | 180K |
| 代理商： | PZ5128-S10BE-S |
Philips Semiconductors
Product specification
PZ5128
128 macrocell CPLD
1997 Aug 12
8
JTAG Testing Capability
JTAG is the commonly-used acronym for the Boundary Scan Test
(BST) feature defined for integrated circuits by IEEE Standard
1149.1. This standard defines input/output pins, logic control
functions, and commands which facilitate both board and device
level testing without the use of specialized test equipment. BST
provides the ability to test the external connections of a device, test
the internal logic of the device, and capture data from the device
during normal operation. BST provides a number of benefits in each
of the following areas:
Testability
–
Allows testing of an unlimited number of interconnects on the
printed circuit board
–
Testability is designed in at the component level
–
Enables desired signal levels to be set at specific pins (Preload)
–
Data from pin or core logic signals can be examined during
normal operation
Reliability
–
Eliminates physical contacts common to existing test fixtures
(e.g., “bed-of-nails”)
–
Degradation of test equipment is no longer a concern
–
Facilitates the handling of smaller, surface-mount components
–
Allows for testing when components exist on both sides of the
printed circuit board
Cost
–
Reduces/eliminates the need for expensive test equipment
–
Reduces test preparation time
–
Reduces spare board inventories
The Philips PZ5128’s JTAG interface includes a TAP Port and a TAP
Controller, both of which are defined by the IEEE 1149.1 JTAG
Specification. As implemented in the Philips PZ5128, the TAP Port
includes four of the five pins (refer to Table 3) described in the JTAG
specification: TCK, TMS, TDI, and TDO. The fifth signal defined by
the JTAG specification is TRST* (Test Reset). TRST* is considered
an optional signal, since it is not actually required to perform BST or
ISP. The Philips PZ5128 saves an I/O pin for general purpose use
by not implementing the optional TRST* signal in the JTAG
interface. Instead, the Philips PZ5128 supports the test reset
functionality through the use of its power up reset circuit, which is
included in all Philips CPLDs. The pins associated with the power up
reset circuit should connect to an external pull-up resistor to keep
the JTAG signals from floating when they are not being used.
In the Philips PZ5128, the four mandatory JTAG pins each require a
unique, dedicated pin on the device. However, if JTAG and ISP are
not desired in the end-application, these pins may instead be used
as additional general I/O pins. The decision as to whether these pins
are used for JTAG/ISP or as general I/O is made when the JEDEC
file is generated. If the use of JTAG/ISP is selected, the dedicated
pins are not available for general purpose use. However, unlike
competing CPLD’s, the Philips PZ5128 does allow the macrocell
logic associated with these dedicated pins to be used as buried logic
even when JTAG/ISP is selected. Table 4 defines the dedicated pins
used by the four mandatory JTAG signals for each of the PZ5128
package types.
The JTAG specifications defines two sets of commands to support
boundary-scan testing: high-level commands and low-level
commands. High-level commands are executed via board test
software on an a user test station such as automated test
equipment, a PC, or an engineering workstation (EWS). Each
high-level command comprises a sequence of low level commands.
These low-level commands are executed within the component
under test, and therefore must be implemented as part of the TAP
Controller design. The set of low-level boundary-scan commands
implemented in the Philips PZ5128 is defined in Table 5. By
supporting this set of low-level commands, the PZ5128 allows
execution of all high-level boundary-scan commands.
Table 3. JTAG Pin Description
PIN
NAME
DESCRIPTION
TCK
Test Clock Output
Clock pin to shift the serial data and instructions in and out of the TDI and TDO pins, respectively.
TCK is also used to clock the TAP Controller state machine.
TMS
Test Mode Select
Serial input pin selects the JTAG instruction mode. TMS should be driven high during user mode
operation.
TDI
Test Data Input
Serial input pin for instructions and test data. Data is shifted in on the rising edge of TCK.
TDO
Test Data Output
Serial output pin for instructions and test data. Data is shifted out on the falling edge of TCK. The
signal is tri-stated if data is not being shifted out of the device.
Table 4. PZ5128 JTAG Pinout by Package Type
DEVICE
(PIN NUMBER / MACROCELL #)
TCK
TMS
TDI
TDO
PZ5128
84-pin PLCC
100-pin PQFP
100-pin TQFP
128-pin LQFP
160-pin PQFP
62 / 96 (F15)
64 / 96 (F15)
62 / 96 (F15)
82 / 96 (F15)
99 / 96 (F15)
23 / 48 (C15)
17 / 48 (C15)
15 / 48 (C15)
21 / 48 (C15)
22 / 48 (C15)
14 / 32 (B15)
6 / 32 (B15)
4 / 32 (B15)
8 / 32 (B15)
9 / 32 (B15)
71 / 112 (G15)
75 / 112 (G15)
73 / 112 (G15)
95 / 112 (G15)
112/ 112 (G15)
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