参数资料
型号: QL3025
厂商: QuickLogic Corp.
英文描述: pASIC3 FPGA Combining High Performance and High Density(高性能和高密度相结合的pASIC3现场可编程门阵列)
中文描述: pASIC3 FPGA的结合高性能和高密度(高性能和高密度相结合的pASIC3现场可编程门阵列)
文件页数: 11/14页
文件大小: 239K
代理商: QL3025
8-33
Military Plastic pASIC 3 Family
QL3040 Clock Cells
I/O Cells
Notes:
[7] The array distributed networks consist of 72 half columns and the global distributed networks consist of
76 half columns, each driven by an independent buffer. The number of half columns used does not
affect clock buffer delay. The array clock has up to 14 loads per half column. The global clock has up
to 16 loads per half column.
[8] The following loads are used for tPXZ:
Symbol
Parameter
Propagation Delays (ns)
Loads per Half Column
[7]
3
4
8
1.3
1.3
1.5
0.7
0.7
0.7
0.9
0.9
1.1
1
2
10
1.6
0.7
1.2
12
1.7
0.7
1.3
14
1.8
0.7
1.4
16
1.9
0.7
1.5
tACK
tGCKP
tGCKB
Array Clock Delay
Global Clock Pin Delay
Global Clock Buffer Delay
1.2
0.7
0.8
1.2
0.7
0.8
Symbol
Parameter
Propagation Delays (ns)
Fanout
[5]
2
3
1.6
1.8
3.1
3.1
0.0
0.0
1.0
1.2
0.9
1.1
2.3
2.3
0.0
0.0
1
4
8
10
3.6
3.1
0.0
3.0
2.9
2.3
0.0
tI/O
tISU
tIH
tlOCLK
tlORST
tlESU
tlEH
Input Delay (bidirectional pad)
Input Register Set-Up Time
Input Register Hold Time
Input Register Clock To Q
Input Register Reset Delay
Input Register clock Enable Set-Up Time
Input Register Clock Enable Hold Time
1.3
3.1
0.0
0.7
0.6
2.3
0.0
2.1
3.1
0.0
1.5
1.4
2.3
0.0
3.1
3.1
0.0
2.5
2.4
2.3
0.0
Symbol
Parameter
Propagation Delays (ns)
Output Load Capacitance (pF)
50
75
2.5
3.1
2.6
3.2
1.7
2.2
2.0
2.6
30
2.1
2.2
1.2
1.6
2.0
1.2
100
3.6
3.7
2.8
3.1
150
4.7
4.8
3.9
4.2
tOUTLH
tOUTHL
tPZH
tPZL
tPHZ
tPLZ
Output Delay Low to High
Output Delay High to Low
Output Delay Tri-state to High
Output Delay Tri-state to Low
Output Delay High to Tri-State [8]
Output Delay Low to Tri-State [8]
5 pF
1K
5 pF
1K
tPHZ
tPLZ
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