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| 型号： | QL4058-0PQ208M |
| 厂商： | QUICKLOGIC CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1008 CLBS, 131328 GATES, PQFP208 |
| 封装： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MO-136, QFP-208 |
| 文件页数： | 42/45页 |
| 文件大小： | 1332K |
| 代理商： | QL4058-0PQ208M |
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2007 QuickLogic Corporation
QuickRAM Family Data Sheet Rev. M
6
Table 5: RAM Cell Synchronous Read Timing
Symbol
Parameter
Propagation Delays (ns) Fanout
1
2
3
4
5
t
SRA
RA Setup Time to RCLK
1.0
t
HRA
RA Hold Time to RCLK
0.0
t
SRE
RE Setup Time to RCLK
1.0
t
HRE
RE Hold Time to RCLK
0.0
t
RCRD
RCLK to RDa
a. Stated timing for worst case Propagation Delay over process variation at V
CC = 3.3 V and TA = 25°C. Multiply by the appropriate
Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range.
4.04.3
4.64.9
6.1
Table 6: RAM Cell Asynchronous Read Timing
Symbol
Parameter
Propagation Delays (ns) Fanout
1
2
3
4
5
RPDRD
RA to RDa
a. Stated timing for worst case Propagation Delay over process variation at V
CC = 3.3 V and TA = 25°C. Multiply by the appropriate
Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range.
3.0
3.3
3.6
3.9
5.1
Table 7: Input-Only/Clock Cells
Symbol
Parameter
Propagation Delays (ns) Fanouta
a. Stated timing for worst case Propagation Delay over process variation at V
CC = 3.3 V and TA = 25°C. Multiply by the appropriate
Delay Factor, K, for speed grade, voltage and temperature settings as specified in
1
2
3
4
8
12
24
t
IN
High Drive Input Delay
1.5
1.6
1.8
1.9
2.4
2.9
4.4
t
INI
High Drive Input, Inverting Delay
1.6
1.7
1.9
2.0
2.5
3.0
4.5
t
ISU
Input Register Set-Up Time
3.1
t
IH
Input Register Hold Time
0.0
t
ICLK
Input Register Clock To Q
0.7
0.8
1.01.1
1.62.1
3.6
t
IRST
Input Register Reset Delay
0.6
0.7
0.9
1.0
1.5
2.0
3.5
t
IESU
Input Register Clock Enable Setup Time
2.3
t
IEH
Input Register Clock Enable Hold Time
0.0
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