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参数资料
| 型号： | QL5432-33APQ208C |
| 英文描述： | ASIC |
| 中文描述： | 专用集成电路 |
| 文件页数： | 7/20页 |
| 文件大小： | 559K |
| 代理商： | QL5432-33APQ208C |
7
QL5432 - QuickPCI
TM
Cfg_CmdReg3
I
Bits 3 from the Command Register in the PCI configuration space (offset 04h). Enable Special Cycle
monitoring. If high, the core reports data parity error in Special Cycles through SERRN if Cfg_CmdReg8
is active.
Bits 4 from the Command Register in the PCI configuration space (offset 04h). Memory Write and Invali-
date (MWI) Enable. If high, the core generates MWI transactions as requested by the backend. Otherwise
it uses Memory Write instead even if MWI is requested.
Bits 6 from the Command Register in the PCI configuration space (offset 04h). Parity Error Response. If
high, the core uses PERRN to report data parity errors. Otherwise it never drives it.
Bits 8 from the Command Register in the PCI configuration space (offset 04h). SERRN Enable. If high,
the cores uses SERRN to report address parity errors if Cfg_CmdReg6 is high.
8-bit value of the Latency Timer in the PCI configuration space (offset 0Ch).
Used when a target read operation should return the value set on the Mst_RdAd[31:0] pins. This select
pin saves on logic which would otherwise need to be used to multiplex Mst_RdAd[31:0] into the
Usr_RdData[31:0] bus. When this signal is asserted, the data on Usr_RdData[31:0] is ignored.
Used when a target read operation should return the value set on the Mst_WrAd[31:0] pins. This select
pin saves on logic which would otherwise need to be used to multiplex Mst_WrAd[31:0] into the
Usr_RdData[31:0] bus. When this signal is asserted, the data on Usr_RdData[31:0] is ignored.
Parity error detected on the PCI bus. When this signal is active, bit 15 of the Status Register must be set
in the PCI configuration space (offset 04h).
System error asserted on the PCI bus. When this signal is active, the Signalled System Error bit, bit 14 of
the Status Register, must be set in the PCI configuration space (offset 04h).
Data parity error detected on the PCI bus by the master. When this signal is active, bit 8 of the Status Reg-
ister must be set in the PCI configuration space (offset 04h).
Inverted copy of the TRDYN signal as driven by the PCI target interface. Valid only within a target access.
Inverted copy of the STOPN signal as driven by the PCI target interface. Valid only within a target access.
Inverted copy of the DEVSELN signal as driven by the PCI target interface. Valid only within a target
access.
Active one clock cycle after the last data phase (may not with data transfer) occurs on PCI and inactive
one clock cycle afterwards.
Used to delay (add wait states to) a target PCI transaction when the backend needs additional time to pro-
vide data (read) or accept data (write). Subject to PCI latency restrictions.
Used to prematurely stop a PCI target access on the next PCI clock.
Used to signal Target Abort on PCI when the backend has fatal error and is unable to complete a transac-
tion. Rarely used.
Used to signal an interrupt on the PCI bus
Cfg_CmdReg4
I
Cfg_CmdReg6
I
Cfg_CmdReg8
I
Cfg_LatCnt[7:0]
Usr_MstRdAd_Sel
I
I
Usr_MstWrAd_Sel
I
Cfg_PERR_Det
O
Cfg_SERR_Sig
O
Cfg_MstPERR_Det
O
Usr_TRDY
Usr_STOPO
Usr_DEVSEL
O
O
O
Usr_Last_Cycle_D1
O
Usr_Rdy
I
Usr_Stop
Usr_Abort
I
I
Usr_Interrupt
I
PCI_clock
PCI_reset
PCI_IRDYN_D1
PCI_FRAMEN_D1
PCI_DEVSELN_D1
PCI_TRDYN_D1
PCI_STOPN_D1
PCI_IDSEL_D1
O
O
O
O
O
O
O
O
PCI clock.
PCI reset signal.
Copy of the IRDYN signal from the PCI bus, delayed by one clock.
Copy of the FRAMEN signal from the PCI bus, delayed by one clock.
Copy of the DEVSELN signal from the PCI bus, delayed by one clock.
Copy of the TRDYN signal from the PCI bus, delayed by one clock.
Copy of the STOPN signal from the PCI bus, delayed by one clock.
Copy of the IDSEL signal from the PCI bus, delayed by one clock.
PCI Internal Signals
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相关代理商/技术参数 |
参数描述 |
|---|---|
| QL5432-33APQ208C-5846 | 制造商:QuickLogic Corporation 功能描述: |
| QL55M6XD30BQ | 制造商:Banner Engineering 功能描述:QL55M6XD30BQ LUMINESCENCE NPN/PNP M12 20 TO 40mm |
| QL55M6XD50BQ | 制造商:Banner Engineering 功能描述:QL55M6XD50BQ LUMINESCENCE NPN/PNP M12 40 TO 75mm |
| QL564 | 制造商:Aim & Thurlby Thandar Instruments 功能描述:PSU 56V 4A PECISION |
| QL564 SII | 制造商:Aim & Thurlby Thandar Instruments 功能描述:POWER SUPPLY, BENCH, ADJ, 1O/P, 56V, Power Supply Output Type:Adjustable, No. of Outputs:1, Output Voltage Min:0V, Output Voltage Max:56V, Output Current Min:0A, Output Current Max:4A, Power Rating:112W, Input Voltage:115VAC / 230VAC, RoHS Compliant: NA 制造商:TTI (THURLBY THANDAR INSTRUMENTS) 功能描述:POWER SUPPLY, BENCH, ADJ, 1O/P, 56V, Power Supply Output Type:Adjustable, No. of |
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